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mb/system76/cml-u/dt: Make use of chipset devicetree
[coreboot.git] / src / soc / mediatek / mt8195 / pll.c
blob397ff21d4e01eca1c6d39c3a2125c676bd5823c9
1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
2
3 #include <console/console.h>
4 #include <device/mmio.h>
5 #include <delay.h>
6 #include <timer.h>
7
8 #include <soc/addressmap.h>
9 #include <soc/infracfg.h>
10 #include <soc/mcucfg.h>
11 #include <soc/pll.h>
12 #include <soc/spm.h>
13 #include <soc/wdt.h>
14
15 struct mt8195_infracfg_ao_bcrm_regs {
16 u32 reserved1[13];
17 u32 vdnr_dcm_top_infra_ctrl0; /* 0x0034 */
18 };
19 check_member(mt8195_infracfg_ao_bcrm_regs, vdnr_dcm_top_infra_ctrl0, 0x0034);
20 static struct mt8195_infracfg_ao_bcrm_regs *const mt8195_infracfg_ao_bcrm =
21 (void *)INFRACFG_AO_BCRM_BASE;
22
23 struct mt8195_pericfg_ao_regs {
24 u32 reserved1[4];
25 u32 peri_module_sw_cg_0_set; /* 0x0010 */
26 };
27 check_member(mt8195_pericfg_ao_regs, peri_module_sw_cg_0_set, 0x0010);
28 static struct mt8195_pericfg_ao_regs *const mt8195_pericfg_ao = (void *)PERICFG_AO_BASE;
29
30 struct mt8195_scp_adsp_regs {
31 u32 reserved1[96];
32 u32 audiodsp_ck_cg; /* 0x180 */
33 };
34 check_member(mt8195_scp_adsp_regs, audiodsp_ck_cg, 0x0180);
35 static struct mt8195_scp_adsp_regs *const mt8195_scp_adsp =
36 (void *)SCP_ADSP_CFG_BASE;
37
38 enum mux_id {
39 TOP_AXI_SEL,
40 TOP_SPM_SEL,
41 TOP_SCP_SEL,
42 TOP_BUS_AXIMEM_SEL,
43 TOP_VPP_SEL,
44 TOP_ETHDR_SEL,
45 TOP_IPE_SEL,
46 TOP_CAM_SEL,
47 TOP_CCU_SEL,
48 TOP_IMG_SEL,
49 TOP_CAMTM_SEL,
50 TOP_DSP_SEL,
51 TOP_DSP1_SEL,
52 TOP_DSP2_SEL,
53 TOP_DSP3_SEL,
54 TOP_DSP4_SEL,
55 TOP_DSP5_SEL,
56 TOP_DSP6_SEL,
57 TOP_DSP7_SEL,
58 TOP_IPU_IF_SEL,
59 TOP_MFG_SEL,
60 TOP_CAMTG_SEL,
61 TOP_CAMTG2_SEL,
62 TOP_CAMTG3_SEL,
63 TOP_CAMTG4_SEL,
64 TOP_CAMTG5_SEL,
65 TOP_UART_SEL,
66 TOP_SPI_SEL,
67 TOP_SPIS_SEL,
68 TOP_MSDC50_0_H_SEL,
69 TOP_MSDC50_0_SEL,
70 TOP_MSDC30_1_SEL,
71 TOP_MSDC30_2_SEL,
72 TOP_INTDIR_SEL,
73 TOP_AUD_INTBUS_SEL,
74 TOP_AUDIO_H_SEL,
75 TOP_PWRAP_ULPOSC_SEL,
76 TOP_ATB_SEL,
77 TOP_PWRMCU_SEL,
78 TOP_DP_SEL,
79 TOP_EDP_SEL,
80 TOP_DPI_SEL,
81 TOP_DISP_PWM0_SEL,
82 TOP_DISP_PWM1_SEL,
83 TOP_USB_SEL,
84 TOP_SSUSB_XHCI_SEL,
85 TOP_USB_1P_SEL,
86 TOP_SSUSB_XHCI_1P_SEL,
87 TOP_USB_2P_SEL,
88 TOP_SSUSB_XHCI_2P_SEL,
89 TOP_USB_3P_SEL,
90 TOP_SSUSB_XHCI_3P_SEL,
91 TOP_I2C_SEL,
92 TOP_SENINF_SEL,
93 TOP_SENINF1_SEL,
94 TOP_SENINF2_SEL,
95 TOP_SENINF3_SEL,
96 TOP_GCPU_SEL,
97 TOP_DXCC_SEL,
98 TOP_DPMAIF_SEL,
99 TOP_AES_UFSFDE_SEL,
100 TOP_UFS_SEL,
101 TOP_UFS_TICK1US_SEL,
102 TOP_UFS_MP_SAP_SEL,
103 TOP_VENC_SEL,
104 TOP_VDEC_SEL,
105 TOP_PWM_SEL,
106 TOP_MCUPM_SEL,
107 TOP_SPMI_P_MST_SEL,
108 TOP_SPMI_M_MST_SEL,
109 TOP_DVFSRC_SEL,
110 TOP_TL_SEL,
111 TOP_TL_P1_SEL,
112 TOP_AES_MSDCFDE_SEL,
113 TOP_DSI_OCC_SEL,
114 TOP_WPE_VPP_SEL,
115 TOP_HDCP_SEL,
116 TOP_HDCP_24M_SEL,
117 TOP_HD20_DACR_REF_SEL,
118 TOP_HD20_HDCP_C_SEL,
119 TOP_HDMI_XTAL_SEL,
120 TOP_HDMI_APB_SEL,
121 TOP_SNPS_ETH_250M_SEL,
122 TOP_SNPS_ETH_62P4M_PTP_SEL,
123 TOP_SNPS_ETH_50M_RMII_SEL,
124 TOP_DGI_OUT_SEL,
125 TOP_NNA0_SEL,
126 TOP_NNA1_SEL,
127 TOP_ADSP_SEL,
128 TOP_ASM_H_SEL,
129 TOP_ASM_M_SEL,
130 TOP_ASM_L_SEL,
131 TOP_APLL1_SEL,
132 TOP_APLL2_SEL,
133 TOP_APLL3_SEL,
134 TOP_APLL4_SEL,
135 TOP_APLL5_SEL,
136 TOP_I2SO1_M_SEL,
137 TOP_I2SO2_M_SEL,
138 TOP_I2SI1_M_SEL,
139 TOP_I2SI2_M_SEL,
140 TOP_DPTX_M_SEL,
141 TOP_AUD_IEC_SEL,
142 TOP_A1SYS_HP_SEL,
143 TOP_A2SYS_SEL,
144 TOP_A3SYS_SEL,
145 TOP_A4SYS_SEL,
146 TOP_SPINFI_B_SEL,
147 TOP_NFI1X_SEL,
148 TOP_ECC_SEL,
149 TOP_AUDIO_LOCAL_BUS_SEL,
150 TOP_SPINOR_SEL,
151 TOP_DVIO_DGI_REF_SEL,
152 TOP_SRCK_SEL,
153 TOP_RSVD1_SEL,
154 TOP_MFG_FAST_SEL,
155 TOP_NR_MUX
156 };
157
158 #define MUX(_id, _reg, _mux_shift, _mux_width) \
159 [_id] = { \
160 .reg = &mtk_topckgen->_reg, \
161 .mux_shift = _mux_shift, \
162 .mux_width = _mux_width, \
163 }
164
165 #define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\
166 [_id] = { \
167 .reg = &mtk_topckgen->_reg, \
168 .set_reg = &mtk_topckgen->_reg##_set, \
169 .clr_reg = &mtk_topckgen->_reg##_clr, \
170 .mux_shift = _mux_shift, \
171 .mux_width = _mux_width, \
172 .upd_reg = &mtk_topckgen->_upd_reg, \
173 .upd_shift = _upd_shift, \
174 }
175
176 static const struct mux muxes[] = {
177 /* CLK_CFG_0 */
178 MUX_UPD(TOP_AXI_SEL, clk_cfg_0, 0, 3, clk_cfg_update, 0),
179 MUX_UPD(TOP_SPM_SEL, clk_cfg_0, 8, 2, clk_cfg_update, 1),
180 MUX_UPD(TOP_SCP_SEL, clk_cfg_0, 16, 3, clk_cfg_update, 2),
181 MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, 24, 3, clk_cfg_update, 3),
182 /* CLK_CFG_1 */
183 MUX_UPD(TOP_VPP_SEL, clk_cfg_1, 0, 4, clk_cfg_update, 4),
184 MUX_UPD(TOP_ETHDR_SEL, clk_cfg_1, 8, 4, clk_cfg_update, 5),
185 MUX_UPD(TOP_IPE_SEL, clk_cfg_1, 16, 4, clk_cfg_update, 6),
186 MUX_UPD(TOP_CAM_SEL, clk_cfg_1, 24, 4, clk_cfg_update, 7),
187 /* CLK_CFG_2 */
188 MUX_UPD(TOP_CCU_SEL, clk_cfg_2, 0, 4, clk_cfg_update, 8),
189 MUX_UPD(TOP_IMG_SEL, clk_cfg_2, 8, 4, clk_cfg_update, 9),
190 MUX_UPD(TOP_CAMTM_SEL, clk_cfg_2, 16, 2, clk_cfg_update, 10),
191 MUX_UPD(TOP_DSP_SEL, clk_cfg_2, 24, 3, clk_cfg_update, 11),
192 /* CLK_CFG_3 */
193 MUX_UPD(TOP_DSP1_SEL, clk_cfg_3, 0, 3, clk_cfg_update, 12),
194 MUX_UPD(TOP_DSP2_SEL, clk_cfg_3, 8, 3, clk_cfg_update, 13),
195 MUX_UPD(TOP_DSP3_SEL, clk_cfg_3, 16, 3, clk_cfg_update, 14),
196 MUX_UPD(TOP_DSP4_SEL, clk_cfg_3, 24, 3, clk_cfg_update, 15),
197 /* CLK_CFG_4 */
198 MUX_UPD(TOP_DSP5_SEL, clk_cfg_4, 0, 3, clk_cfg_update, 16),
199 MUX_UPD(TOP_DSP6_SEL, clk_cfg_4, 8, 3, clk_cfg_update, 17),
200 MUX_UPD(TOP_DSP7_SEL, clk_cfg_4, 16, 3, clk_cfg_update, 18),
201 MUX_UPD(TOP_IPU_IF_SEL, clk_cfg_4, 24, 3, clk_cfg_update, 19),
202 /* CLK_CFG_5 */
203 MUX_UPD(TOP_MFG_SEL, clk_cfg_5, 0, 2, clk_cfg_update, 20),
204 MUX_UPD(TOP_CAMTG_SEL, clk_cfg_5, 8, 3, clk_cfg_update, 21),
205 MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_5, 16, 3, clk_cfg_update, 22),
206 MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_5, 24, 3, clk_cfg_update, 23),
207 /* CLK_CFG_6 */
208 MUX_UPD(TOP_CAMTG4_SEL, clk_cfg_6, 0, 3, clk_cfg_update, 24),
209 MUX_UPD(TOP_CAMTG5_SEL, clk_cfg_6, 8, 3, clk_cfg_update, 25),
210 MUX_UPD(TOP_UART_SEL, clk_cfg_6, 16, 1, clk_cfg_update, 26),
211 MUX_UPD(TOP_SPI_SEL, clk_cfg_6, 24, 3, clk_cfg_update, 27),
212 /* CLK_CFG_7 */
213 MUX_UPD(TOP_SPIS_SEL, clk_cfg_7, 0, 3, clk_cfg_update, 28),
214 MUX_UPD(TOP_MSDC50_0_H_SEL, clk_cfg_7, 8, 2, clk_cfg_update, 29),
215 MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_7, 16, 3, clk_cfg_update, 30),
216 MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_7, 24, 3, clk_cfg_update, 31),
217 /* CLK_CFG_8 */
218 MUX_UPD(TOP_MSDC30_2_SEL, clk_cfg_8, 0, 3, clk_cfg_update1, 0),
219 MUX_UPD(TOP_INTDIR_SEL, clk_cfg_8, 8, 2, clk_cfg_update1, 1),
220 MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_8, 16, 2, clk_cfg_update1, 2),
221 MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_8, 24, 2, clk_cfg_update1, 3),
222 /* CLK_CFG_9 */
223 MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_9, 0, 3, clk_cfg_update1, 4),
224 MUX_UPD(TOP_ATB_SEL, clk_cfg_9, 8, 2, clk_cfg_update1, 5),
225 MUX_UPD(TOP_PWRMCU_SEL, clk_cfg_9, 16, 3, clk_cfg_update1, 6),
226 MUX_UPD(TOP_DP_SEL, clk_cfg_9, 24, 4, clk_cfg_update1, 7),
227 /* CLK_CFG_10 */
228 MUX_UPD(TOP_EDP_SEL, clk_cfg_10, 0, 4, clk_cfg_update1, 8),
229 MUX_UPD(TOP_DPI_SEL, clk_cfg_10, 8, 4, clk_cfg_update1, 9),
230 MUX_UPD(TOP_DISP_PWM0_SEL, clk_cfg_10, 16, 3, clk_cfg_update1, 10),
231 MUX_UPD(TOP_DISP_PWM1_SEL, clk_cfg_10, 24, 3, clk_cfg_update1, 11),
232 /* CLK_CFG_11 */
233 MUX_UPD(TOP_USB_SEL, clk_cfg_11, 0, 2, clk_cfg_update1, 12),
234 MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_11, 8, 2, clk_cfg_update1, 13),
235 MUX_UPD(TOP_USB_1P_SEL, clk_cfg_11, 16, 2, clk_cfg_update1, 14),
236 MUX_UPD(TOP_SSUSB_XHCI_1P_SEL, clk_cfg_11, 24, 2, clk_cfg_update1, 15),
237 /* CLK_CFG_12 */
238 MUX_UPD(TOP_USB_2P_SEL, clk_cfg_12, 0, 2, clk_cfg_update1, 16),
239 MUX_UPD(TOP_SSUSB_XHCI_2P_SEL, clk_cfg_12, 8, 2, clk_cfg_update1, 17),
240 MUX_UPD(TOP_USB_3P_SEL, clk_cfg_12, 16, 2, clk_cfg_update1, 18),
241 MUX_UPD(TOP_SSUSB_XHCI_3P_SEL, clk_cfg_12, 24, 2, clk_cfg_update1, 19),
242 /* CLK_CFG_13 */
243 MUX_UPD(TOP_I2C_SEL, clk_cfg_13, 0, 2, clk_cfg_update1, 20),
244 MUX_UPD(TOP_SENINF_SEL, clk_cfg_13, 8, 3, clk_cfg_update1, 21),
245 MUX_UPD(TOP_SENINF1_SEL, clk_cfg_13, 16, 3, clk_cfg_update1, 22),
246 MUX_UPD(TOP_SENINF2_SEL, clk_cfg_13, 24, 3, clk_cfg_update1, 23),
247 /* CLK_CFG_14 */
248 MUX_UPD(TOP_SENINF3_SEL, clk_cfg_14, 0, 3, clk_cfg_update1, 24),
249 MUX_UPD(TOP_GCPU_SEL, clk_cfg_14, 8, 3, clk_cfg_update1, 25),
250 MUX_UPD(TOP_DXCC_SEL, clk_cfg_14, 16, 2, clk_cfg_update1, 26),
251 MUX_UPD(TOP_DPMAIF_SEL, clk_cfg_14, 24, 3, clk_cfg_update1, 27),
252 /* CLK_CFG_15 */
253 MUX_UPD(TOP_AES_UFSFDE_SEL, clk_cfg_15, 0, 3, clk_cfg_update1, 28),
254 MUX_UPD(TOP_UFS_SEL, clk_cfg_15, 8, 3, clk_cfg_update1, 29),
255 MUX_UPD(TOP_UFS_TICK1US_SEL, clk_cfg_15, 16, 1, clk_cfg_update1, 30),
256 MUX_UPD(TOP_UFS_MP_SAP_SEL, clk_cfg_15, 24, 1, clk_cfg_update1, 31),
257 /* CLK_CFG_16 */
258 MUX_UPD(TOP_VENC_SEL, clk_cfg_16, 0, 4, clk_cfg_update2, 0),
259 MUX_UPD(TOP_VDEC_SEL, clk_cfg_16, 8, 4, clk_cfg_update2, 1),
260 MUX_UPD(TOP_PWM_SEL, clk_cfg_16, 16, 1, clk_cfg_update2, 2),
261 MUX_UPD(TOP_MCUPM_SEL, clk_cfg_16, 24, 2, clk_cfg_update2, 3),
262 /* CLK_CFG_17 */
263 MUX_UPD(TOP_SPMI_P_MST_SEL, clk_cfg_17, 0, 4, clk_cfg_update2, 4),
264 MUX_UPD(TOP_SPMI_M_MST_SEL, clk_cfg_17, 8, 4, clk_cfg_update2, 5),
265 MUX_UPD(TOP_DVFSRC_SEL, clk_cfg_17, 16, 2, clk_cfg_update2, 6),
266 MUX_UPD(TOP_TL_SEL, clk_cfg_17, 24, 2, clk_cfg_update2, 7),
267 /* CLK_CFG_18 */
268 MUX_UPD(TOP_TL_P1_SEL, clk_cfg_18, 0, 2, clk_cfg_update2, 8),
269 MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_18, 8, 3, clk_cfg_update2, 9),
270 MUX_UPD(TOP_DSI_OCC_SEL, clk_cfg_18, 16, 2, clk_cfg_update2, 10),
271 MUX_UPD(TOP_WPE_VPP_SEL, clk_cfg_18, 24, 4, clk_cfg_update2, 11),
272 /* CLK_CFG_19 */
273 MUX_UPD(TOP_HDCP_SEL, clk_cfg_19, 0, 2, clk_cfg_update2, 12),
274 MUX_UPD(TOP_HDCP_24M_SEL, clk_cfg_19, 8, 2, clk_cfg_update2, 13),
275 MUX_UPD(TOP_HD20_DACR_REF_SEL, clk_cfg_19, 16, 2, clk_cfg_update2, 14),
276 MUX_UPD(TOP_HD20_HDCP_C_SEL, clk_cfg_19, 24, 2, clk_cfg_update2, 15),
277 /* CLK_CFG_20 */
278 MUX_UPD(TOP_HDMI_XTAL_SEL, clk_cfg_20, 0, 1, clk_cfg_update2, 16),
279 MUX_UPD(TOP_HDMI_APB_SEL, clk_cfg_20, 8, 2, clk_cfg_update2, 17),
280 MUX_UPD(TOP_SNPS_ETH_250M_SEL, clk_cfg_20, 16, 1, clk_cfg_update2, 18),
281 MUX_UPD(TOP_SNPS_ETH_62P4M_PTP_SEL, clk_cfg_20, 24, 2, clk_cfg_update2, 19),
282 /* CLK_CFG_21 */
283 MUX_UPD(TOP_SNPS_ETH_50M_RMII_SEL, clk_cfg_21, 0, 1, clk_cfg_update2, 20),
284 MUX_UPD(TOP_DGI_OUT_SEL, clk_cfg_21, 8, 3, clk_cfg_update2, 21),
285 MUX_UPD(TOP_NNA0_SEL, clk_cfg_21, 16, 4, clk_cfg_update2, 22),
286 MUX_UPD(TOP_NNA1_SEL, clk_cfg_21, 24, 4, clk_cfg_update2, 23),
287 /* CLK_CFG_22 */
288 MUX_UPD(TOP_ADSP_SEL, clk_cfg_22, 0, 4, clk_cfg_update2, 24),
289 MUX_UPD(TOP_ASM_H_SEL, clk_cfg_22, 8, 2, clk_cfg_update2, 25),
290 MUX_UPD(TOP_ASM_M_SEL, clk_cfg_22, 16, 2, clk_cfg_update2, 26),
291 MUX_UPD(TOP_ASM_L_SEL, clk_cfg_22, 24, 2, clk_cfg_update2, 27),
292 /* CLK_CFG_23 */
293 MUX_UPD(TOP_APLL1_SEL, clk_cfg_23, 0, 1, clk_cfg_update2, 28),
294 MUX_UPD(TOP_APLL2_SEL, clk_cfg_23, 8, 1, clk_cfg_update2, 29),
295 MUX_UPD(TOP_APLL3_SEL, clk_cfg_23, 16, 1, clk_cfg_update2, 30),
296 MUX_UPD(TOP_APLL4_SEL, clk_cfg_23, 24, 1, clk_cfg_update2, 31),
297 /* CLK_CFG_24 */
298 MUX_UPD(TOP_APLL5_SEL, clk_cfg_24, 0, 1, clk_cfg_update3, 0),
299 MUX_UPD(TOP_I2SO1_M_SEL, clk_cfg_24, 8, 3, clk_cfg_update3, 1),
300 MUX_UPD(TOP_I2SO2_M_SEL, clk_cfg_24, 16, 3, clk_cfg_update3, 2),
301 /* CLK_CFG_25 */
302 MUX_UPD(TOP_I2SI1_M_SEL, clk_cfg_25, 8, 3, clk_cfg_update3, 5),
303 MUX_UPD(TOP_I2SI2_M_SEL, clk_cfg_25, 16, 3, clk_cfg_update3, 6),
304 /* CLK_CFG_26 */
305 MUX_UPD(TOP_DPTX_M_SEL, clk_cfg_26, 8, 3, clk_cfg_update3, 9),
306 MUX_UPD(TOP_AUD_IEC_SEL, clk_cfg_26, 16, 3, clk_cfg_update3, 10),
307 MUX_UPD(TOP_A1SYS_HP_SEL, clk_cfg_26, 24, 1, clk_cfg_update3, 11),
308 /* CLK_CFG_27 */
309 MUX_UPD(TOP_A2SYS_SEL, clk_cfg_27, 0, 1, clk_cfg_update3, 12),
310 MUX_UPD(TOP_A3SYS_SEL, clk_cfg_27, 8, 3, clk_cfg_update3, 13),
311 MUX_UPD(TOP_A4SYS_SEL, clk_cfg_27, 16, 3, clk_cfg_update3, 14),
312 MUX_UPD(TOP_SPINFI_B_SEL, clk_cfg_27, 24, 3, clk_cfg_update3, 15),
313 /* CLK_CFG_28 */
314 MUX_UPD(TOP_NFI1X_SEL, clk_cfg_28, 0, 3, clk_cfg_update3, 16),
315 MUX_UPD(TOP_ECC_SEL, clk_cfg_28, 8, 3, clk_cfg_update3, 17),
316 MUX_UPD(TOP_AUDIO_LOCAL_BUS_SEL, clk_cfg_28, 16, 4, clk_cfg_update3, 18),
317 MUX_UPD(TOP_SPINOR_SEL, clk_cfg_28, 24, 2, clk_cfg_update3, 19),
318 /* CLK_CFG_29 */
319 MUX_UPD(TOP_DVIO_DGI_REF_SEL, clk_cfg_29, 0, 3, clk_cfg_update3, 20),
320 MUX_UPD(TOP_SRCK_SEL, clk_cfg_29, 24, 1, clk_cfg_update3, 23),
321 /* CLK_CFG_37 */
322 MUX_UPD(TOP_RSVD1_SEL, clk_cfg_37, 0, 3, clk_cfg_update4, 20),
323 /* CLK_MISC_CFG_3 */
324 MUX(TOP_MFG_FAST_SEL, clk_misc_cfg_3, 8, 1),
325 };
326
327 struct mux_sel {
328 enum mux_id id;
329 u32 sel;
330 };
331
332 static const struct mux_sel mux_sels[] = {
333 /* CLK_CFG_0 */
334 { .id = TOP_AXI_SEL, .sel = 2 }, /* 2: mainpll_d7_d2 */
335 /* CLK_CFG_37 */
336 { .id = TOP_RSVD1_SEL, .sel = 2 }, /* 2: mainpll_d5_d4 */
337 /* CLK_CFG_0 */
338 { .id = TOP_SPM_SEL, .sel = 2 }, /* 2: mainpll_d7_d4 */
339 { .id = TOP_SCP_SEL, .sel = 7 }, /* 7: mainpll_d6_d2 */
340 { .id = TOP_BUS_AXIMEM_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */
341 /* CLK_CFG_1 */
342 { .id = TOP_VPP_SEL, .sel = 9 }, /* 9: mainpll_d4 */
343 { .id = TOP_ETHDR_SEL, .sel = 8 }, /* 8: univpll_d6 */
344 { .id = TOP_IPE_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */
345 { .id = TOP_CAM_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */
346 /* CLK_CFG_2 */
347 { .id = TOP_CCU_SEL, .sel = 2 }, /* 2: mainpll_d4_d2 */
348 { .id = TOP_IMG_SEL, .sel = 11 }, /* 11: univpll_d5_d2 */
349 { .id = TOP_CAMTM_SEL, .sel = 2 }, /* 2: univpll_d6_d2 */
350 { .id = TOP_DSP_SEL, .sel = 7 }, /* 7: univpll_d3 */
351 /* CLK_CFG_3 */
352 { .id = TOP_DSP1_SEL, .sel = 7 }, /* 7: univpll_d3 */
353 { .id = TOP_DSP2_SEL, .sel = 7 }, /* 7: univpll_d3 */
354 { .id = TOP_DSP3_SEL, .sel = 7 }, /* 7: univpll_d3 */
355 { .id = TOP_DSP4_SEL, .sel = 7 }, /* 7: univpll_d3 */
356 /* CLK_CFG_4 */
357 { .id = TOP_DSP5_SEL, .sel = 7 }, /* 7: univpll_d3 */
358 { .id = TOP_DSP6_SEL, .sel = 7 }, /* 7: univpll_d3 */
359 { .id = TOP_DSP7_SEL, .sel = 7 }, /* 7: univpll_d3 */
360 { .id = TOP_IPU_IF_SEL, .sel = 7 }, /* 7: mmpll_d4 */
361 /* CLK_CFG_5 */
362 { .id = TOP_MFG_SEL, .sel = 3 }, /* 3: univpll_d7 */
363 { .id = TOP_CAMTG_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */
364 { .id = TOP_CAMTG2_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */
365 { .id = TOP_CAMTG3_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */
366 /* CLK_CFG_6 */
367 { .id = TOP_CAMTG4_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */
368 { .id = TOP_CAMTG5_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */
369 { .id = TOP_UART_SEL, .sel = 0 }, /* 0: xtal_26m_ck */
370 { .id = TOP_SPI_SEL, .sel = 4 }, /* 4: univpll_d6_d2 */
371 /* CLK_CFG_7 */
372 { .id = TOP_SPIS_SEL, .sel = 1 }, /* 1: univpll_d6 */
373 { .id = TOP_MSDC50_0_H_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */
374 { .id = TOP_MSDC50_0_SEL, .sel = 1 }, /* 1: msdcpll_ck */
375 { .id = TOP_MSDC30_1_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */
376 /* CLK_CFG_8 */
377 { .id = TOP_MSDC30_2_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */
378 { .id = TOP_INTDIR_SEL, .sel = 3 }, /* 3: univpll_d4 */
379 { .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: mainpll_d4_d4 */
380 { .id = TOP_AUDIO_H_SEL, .sel = 2 }, /* 2: apll1_ck */
381 /* CLK_CFG_9 */
382 { .id = TOP_PWRAP_ULPOSC_SEL, .sel = 1 }, /* 1: clk26m */
383 { .id = TOP_ATB_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */
384 { .id = TOP_PWRMCU_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */
385 { .id = TOP_DP_SEL, .sel = 3 }, /* 3: tvdpll1_d4 */
386 /* CLK_CFG_10 */
387 { .id = TOP_EDP_SEL, .sel = 3 }, /* 3: tvdpll1_d4 */
388 { .id = TOP_DPI_SEL, .sel = 1 }, /* 1: tvdpll1_d2 */
389 { .id = TOP_DISP_PWM0_SEL, .sel = 1 }, /* 1: univpll_d6_d4 */
390 { .id = TOP_DISP_PWM1_SEL, .sel = 1 }, /* 1: univpll_d6_d4 */
391 /* CLK_CFG_11 */
392 { .id = TOP_USB_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
393 { .id = TOP_SSUSB_XHCI_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
394 { .id = TOP_USB_1P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
395 { .id = TOP_SSUSB_XHCI_1P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
396 /* CLK_CFG_12 */
397 { .id = TOP_USB_2P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
398 { .id = TOP_SSUSB_XHCI_2P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
399 { .id = TOP_USB_3P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
400 { .id = TOP_SSUSB_XHCI_3P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
401 /* CLK_CFG_13 */
402 { .id = TOP_I2C_SEL, .sel = 2 }, /* 2: univpll_d5_d4 */
403 { .id = TOP_SENINF_SEL, .sel = 4 }, /* 4: univpll_d7 */
404 { .id = TOP_SENINF1_SEL, .sel = 4 }, /* 4: univpll_d7 */
405 { .id = TOP_SENINF2_SEL, .sel = 4 }, /* 4: univpll_d7 */
406 /* CLK_CFG_14 */
407 { .id = TOP_SENINF3_SEL, .sel = 4 }, /* 4: univpll_d7 */
408 { .id = TOP_GCPU_SEL, .sel = 3 }, /* 3: mmpll_d5_d2 */
409 { .id = TOP_DXCC_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */
410 { .id = TOP_DPMAIF_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */
411 /* CLK_CFG_15 */
412 { .id = TOP_AES_UFSFDE_SEL, .sel = 5 }, /* 5: univpll_d6 */
413 { .id = TOP_UFS_SEL, .sel = 6 }, /* 6: msdcpll_d2 */
414 { .id = TOP_UFS_TICK1US_SEL, .sel = 0 }, /* 0: xtal_26m_d52 */
415 { .id = TOP_UFS_MP_SAP_SEL, .sel = 0 }, /* 0: xtal_26m_ck */
416 /* CLK_CFG_16 */
417 { .id = TOP_VENC_SEL, .sel = 14 }, /* 14: univpll_d5_d2 */
418 { .id = TOP_VDEC_SEL, .sel = 1 }, /* 1: mainpll_d5_d2 */
419 { .id = TOP_PWM_SEL, .sel = 1 }, /* 1: univpll_d4_d8 */
420 { .id = TOP_MCUPM_SEL, .sel = 1 }, /* 1: mainpll_d6_d2 */
421 /* CLK_CFG_17 */
422 { .id = TOP_SPMI_P_MST_SEL, .sel = 7 }, /* 7: mainpll_d7_d8 */
423 { .id = TOP_SPMI_M_MST_SEL, .sel = 7 }, /* 7: mainpll_d7_d8 */
424 { .id = TOP_DVFSRC_SEL, .sel = 0 }, /* 0: xtal_26m_ck */
425 { .id = TOP_TL_SEL, .sel = 2 }, /* 2: mainpll_d4_d4 */
426 /* CLK_CFG_18 */
427 { .id = TOP_TL_P1_SEL, .sel = 2 }, /* 2: mainpll_d4_d4 */
428 { .id = TOP_AES_MSDCFDE_SEL, .sel = 5 }, /* 5: univpll_d6 */
429 { .id = TOP_DSI_OCC_SEL, .sel = 1 }, /* 1: mainpll_d6_d2 */
430 { .id = TOP_WPE_VPP_SEL, .sel = 4 }, /* 4: mainpll_d4_d2 */
431 /* CLK_CFG_19 */
432 { .id = TOP_HDCP_SEL, .sel = 3 }, /* 3: univpll_d6_d4 */
433 { .id = TOP_HDCP_24M_SEL, .sel = 2 }, /* 2: univpll_192m_d8 */
434 { .id = TOP_HD20_DACR_REF_SEL, .sel = 1 }, /* 1: univpll_d4_d2 */
435 { .id = TOP_HD20_HDCP_C_SEL, .sel = 1 }, /* 1: msdcpll_d4 */
436 /* CLK_CFG_20 */
437 { .id = TOP_HDMI_XTAL_SEL, .sel = 0 }, /* 0: xtal_26m_ck */
438 { .id = TOP_HDMI_APB_SEL, .sel = 2 }, /* 2: msdcpll_d2 */
439 { .id = TOP_SNPS_ETH_250M_SEL, .sel = 1 }, /* 1: ethpll_d2 */
440 { .id = TOP_SNPS_ETH_62P4M_PTP_SEL, .sel = 3 }, /* 3: ethpll_d8 */
441 /* CLK_CFG_21 */
442 { .id = TOP_SNPS_ETH_50M_RMII_SEL, .sel = 1 }, /* 1: ethpll_d10 */
443 { .id = TOP_DGI_OUT_SEL, .sel = 5 }, /* 5: mmpll_d4_d4 */
444 { .id = TOP_NNA0_SEL, .sel = 1 }, /* 1: nnapll_ck */
445 { .id = TOP_NNA1_SEL, .sel = 1 }, /* 1: nnapll_ck */
446 /* CLK_CFG_22 */
447 { .id = TOP_ADSP_SEL, .sel = 8 }, /* 8: adsppll_ck */
448 { .id = TOP_ASM_H_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */
449 { .id = TOP_ASM_M_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */
450 { .id = TOP_ASM_L_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */
451 /* CLK_CFG_23 */
452 { .id = TOP_APLL1_SEL, .sel = 1 }, /* 1: apll1_d4 */
453 { .id = TOP_APLL2_SEL, .sel = 1 }, /* 1: apll2_d4 */
454 { .id = TOP_APLL3_SEL, .sel = 1 }, /* 1: apll3_d4 */
455 { .id = TOP_APLL4_SEL, .sel = 1 }, /* 1: apll4_d4 */
456 /* CLK_CFG_24 */
457 { .id = TOP_APLL5_SEL, .sel = 1 }, /* 1: apll5_d4 */
458 { .id = TOP_I2SO1_M_SEL, .sel = 6 }, /* 6: hdmirx_apll_ck */
459 { .id = TOP_I2SO2_M_SEL, .sel = 6 }, /* 6: hdmirx_apll_ck */
460 /* CLK_CFG_25 */
461 { .id = TOP_I2SI1_M_SEL, .sel = 6 }, /* 6: hdmirx_apll_ck */
462 { .id = TOP_I2SI2_M_SEL, .sel = 6 }, /* 6: hdmirx_apll_ck */
463 /* CLK_CFG_26 */
464 { .id = TOP_DPTX_M_SEL, .sel = 6 }, /* 6: hdmirx_apll_ck */
465 { .id = TOP_AUD_IEC_SEL, .sel = 6 }, /* 6: hdmirx_apll_ck */
466 { .id = TOP_A1SYS_HP_SEL, .sel = 1 }, /* 1: apll1_d4 */
467 /* CLK_CFG_27 */
468 { .id = TOP_A2SYS_SEL, .sel = 1 }, /* 1: apll2_d4 */
469 { .id = TOP_A3SYS_SEL, .sel = 1 }, /* 1: apll3_d4 */
470 { .id = TOP_A4SYS_SEL, .sel = 2 }, /* 2: apll4_d4 */
471 { .id = TOP_SPINFI_B_SEL, .sel = 7 }, /* 7: univpll_d5_d4 */
472 /* CLK_CFG_28 */
473 { .id = TOP_NFI1X_SEL, .sel = 7 }, /* 7: mainpll_d6_d2 */
474 { .id = TOP_ECC_SEL, .sel = 1 }, /* 1: mainpll_d4_d4 */
475 { .id = TOP_AUDIO_LOCAL_BUS_SEL, .sel = 3 }, /* 3: mainpll_d7_d2 */
476 { .id = TOP_SPINOR_SEL, .sel = 3 }, /* 3: univpll_d6_d8 */
477 /* CLK_CFG_29 */
478 { .id = TOP_DVIO_DGI_REF_SEL, .sel = 1 }, /* 1: in_dgi_ck */
479 { .id = TOP_SRCK_SEL, .sel = 0 }, /* 0: ulposc_d10 */
480 /* CLK_MISC_CFG_3 */
481 { .id = TOP_MFG_FAST_SEL, .sel = 1 }, /* 1: AD_MFGPLL_OPP_CK */
482 };
483
484 enum pll_id {
485 APMIXED_ARMPLL_LL,
486 APMIXED_ARMPLL_BL,
487 APMIXED_CCIPLL,
488 APMIXED_NNAPLL,
489 APMIXED_RESPLL,
490 APMIXED_ETHPLL,
491 APMIXED_MSDCPLL,
492 APMIXED_TVDPLL1,
493 APMIXED_TVDPLL2,
494 APMIXED_MMPLL,
495 APMIXED_MAINPLL,
496 APMIXED_VDECPLL,
497 APMIXED_IMGPLL,
498 APMIXED_UNIVPLL,
499 APMIXED_HDMIPLL1,
500 APMIXED_HDMIPLL2,
501 APMIXED_HDMIRX_APLL,
502 APMIXED_USB1PLL,
503 APMIXED_ADSPPLL,
504 APMIXED_APLL1,
505 APMIXED_APLL2,
506 APMIXED_APLL3,
507 APMIXED_APLL4,
508 APMIXED_APLL5,
509 APMIXED_MFGPLL,
510 APMIXED_DGIPLL,
511 APMIXED_PLL_MAX
512 };
513
514 static const u32 pll_div_rate[] = {
515 3800UL * MHz,
516 1900 * MHz,
517 950 * MHz,
518 475 * MHz,
519 237500 * KHz,
520 0,
521 };
522
523 static const struct pll plls[] = {
524 PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con4,
525 NO_RSTB_SHIFT, 22, armpll_ll_con2, 24, armpll_ll_con2, 0,
526 pll_div_rate),
527 PLL(APMIXED_ARMPLL_BL, armpll_bl_con0, armpll_bl_con4,
528 NO_RSTB_SHIFT, 22, armpll_bl_con2, 24, armpll_bl_con2, 0,
529 pll_div_rate),
530 PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con4,
531 NO_RSTB_SHIFT, 22, ccipll_con2, 24, ccipll_con2, 0,
532 pll_div_rate),
533 PLL(APMIXED_NNAPLL, nnapll_con0, nnapll_con4,
534 NO_RSTB_SHIFT, 22, nnapll_con2, 24, nnapll_con2, 0,
535 pll_div_rate),
536 PLL(APMIXED_RESPLL, respll_con0, respll_con4,
537 NO_RSTB_SHIFT, 22, respll_con2, 24, respll_con2, 0,
538 pll_div_rate),
539 PLL(APMIXED_ETHPLL, ethpll_con0, ethpll_con4,
540 NO_RSTB_SHIFT, 22, ethpll_con2, 24, ethpll_con2, 0,
541 pll_div_rate),
542 PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con4,
543 NO_RSTB_SHIFT, 22, msdcpll_con2, 24, msdcpll_con2, 0,
544 pll_div_rate),
545 PLL(APMIXED_TVDPLL1, tvdpll1_con0, tvdpll1_con4,
546 NO_RSTB_SHIFT, 22, tvdpll1_con2, 24, tvdpll1_con2, 0,
547 pll_div_rate),
548 PLL(APMIXED_TVDPLL2, tvdpll2_con0, tvdpll2_con4,
549 NO_RSTB_SHIFT, 22, tvdpll2_con2, 24, tvdpll2_con2, 0,
550 pll_div_rate),
551 PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con4,
552 23, 22, mmpll_con2, 24, mmpll_con2, 0,
553 pll_div_rate),
554 PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con4,
555 23, 22, mainpll_con2, 24, mainpll_con2, 0,
556 pll_div_rate),
557 PLL(APMIXED_VDECPLL, vdecpll_con0, vdecpll_con4,
558 NO_RSTB_SHIFT, 22, vdecpll_con2, 24, vdecpll_con2, 0,
559 pll_div_rate),
560 PLL(APMIXED_IMGPLL, imgpll_con0, imgpll_con4,
561 NO_RSTB_SHIFT, 22, imgpll_con2, 24, imgpll_con2, 0,
562 pll_div_rate),
563 PLL(APMIXED_UNIVPLL, univpll_con0, univpll_con4,
564 23, 22, univpll_con2, 24, univpll_con2, 0,
565 pll_div_rate),
566 PLL(APMIXED_HDMIPLL1, hdmipll1_con0, hdmipll1_con4,
567 NO_RSTB_SHIFT, 22, hdmipll1_con2, 24, hdmipll1_con2, 0,
568 pll_div_rate),
569 PLL(APMIXED_HDMIPLL2, hdmipll2_con0, hdmipll2_con4,
570 NO_RSTB_SHIFT, 22, hdmipll2_con2, 24, hdmipll2_con2, 0,
571 pll_div_rate),
572 PLL(APMIXED_HDMIRX_APLL, hdmirx_apll_con0, hdmirx_apll_con5,
573 NO_RSTB_SHIFT, 32, hdmirx_apll_con2, 24, hdmirx_apll_con3, 0,
574 pll_div_rate),
575 PLL(APMIXED_USB1PLL, usb1pll_con0, usb1pll_con4,
576 NO_RSTB_SHIFT, 22, usb1pll_con2, 24, usb1pll_con2, 0,
577 pll_div_rate),
578 PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con4,
579 NO_RSTB_SHIFT, 22, adsppll_con2, 24, adsppll_con2, 0,
580 pll_div_rate),
581 PLL(APMIXED_APLL1, apll1_con0, apll1_con5,
582 NO_RSTB_SHIFT, 32, apll1_con2, 24, apll1_con3, 0,
583 pll_div_rate),
584 PLL(APMIXED_APLL2, apll2_con0, apll2_con5,
585 NO_RSTB_SHIFT, 32, apll2_con2, 24, apll2_con3, 0,
586 pll_div_rate),
587 PLL(APMIXED_APLL3, apll3_con0, apll3_con5,
588 NO_RSTB_SHIFT, 32, apll3_con2, 24, apll3_con3, 0,
589 pll_div_rate),
590 PLL(APMIXED_APLL4, apll4_con0, apll4_con5,
591 NO_RSTB_SHIFT, 32, apll4_con2, 24, apll4_con3, 0,
592 pll_div_rate),
593 PLL(APMIXED_APLL5, apll5_con0, apll5_con5,
594 NO_RSTB_SHIFT, 32, apll5_con2, 24, apll5_con3, 0,
595 pll_div_rate),
596 PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con4,
597 NO_RSTB_SHIFT, 22, mfgpll_con2, 24, mfgpll_con2, 0,
598 pll_div_rate),
599 PLL(APMIXED_DGIPLL, dgipll_con0, dgipll_con4,
600 NO_RSTB_SHIFT, 22, dgipll_con2, 24, dgipll_con2, 0,
601 pll_div_rate),
602 };
603
604 struct rate {
605 enum pll_id id;
606 u32 rate;
607 };
608
609 static const struct rate rates[] = {
610 { .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ },
611 { .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ },
612 { .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ },
613 { .id = APMIXED_NNAPLL, .rate = NNAPLL_HZ },
614 { .id = APMIXED_RESPLL, .rate = RESPLL_HZ },
615 { .id = APMIXED_ETHPLL, .rate = ETHPLL_HZ },
616 { .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ },
617 { .id = APMIXED_TVDPLL1, .rate = TVDPLL1_HZ },
618 { .id = APMIXED_TVDPLL2, .rate = TVDPLL2_HZ },
619 { .id = APMIXED_MMPLL, .rate = MMPLL_HZ },
620 { .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ },
621 { .id = APMIXED_VDECPLL, .rate = VDECPLL_HZ },
622 { .id = APMIXED_IMGPLL, .rate = IMGPLL_HZ },
623 { .id = APMIXED_UNIVPLL, .rate = UNIVPLL_HZ },
624 { .id = APMIXED_HDMIPLL1, .rate = HDMIPLL1_HZ },
625 { .id = APMIXED_HDMIPLL2, .rate = HDMIPLL2_HZ },
626 { .id = APMIXED_HDMIRX_APLL, .rate = HDMIRX_APLL_HZ },
627 { .id = APMIXED_USB1PLL, .rate = USB1PLL_HZ },
628 { .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ },
629 { .id = APMIXED_APLL1, .rate = APLL1_HZ },
630 { .id = APMIXED_APLL2, .rate = APLL2_HZ },
631 { .id = APMIXED_APLL3, .rate = APLL3_HZ },
632 { .id = APMIXED_APLL4, .rate = APLL4_HZ },
633 { .id = APMIXED_APLL5, .rate = APLL5_HZ },
634 { .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ },
635 { .id = APMIXED_DGIPLL, .rate = DGIPLL_HZ },
636 };
637
638 void pll_set_pcw_change(const struct pll *pll)
639 {
640 setbits32(pll->div_reg, PLL_PCW_CHG);
641 }
642
643 void mt_pll_init(void)
644 {
645 int i;
646
647 /* enable clock square */
648 setbits32(&mtk_apmixed->ap_pll_con0, BIT(2));
649
650 udelay(PLL_CKSQ_ON_DELAY);
651
652 /* enable clock square1 low-pass filter */
653 setbits32(&mtk_apmixed->ap_pll_con0, BIT(1));
654
655 /*
656 * BIT(3): 1 for register control; 0 for sleep control
657 * BIT(8): 1 to enable clock square2; 0 to disable it
658 */
659 clrbits32(&mtk_apmixed->ap_pll_con0, BIT(3) | BIT(8));
660
661 /* xPLL PWR ON */
662 for (i = 0; i < APMIXED_PLL_MAX; i++)
663 setbits32(plls[i].pwr_reg, PLL_PWR_ON);
664
665 udelay(PLL_PWR_ON_DELAY);
666
667 /* xPLL ISO Disable */
668 for (i = 0; i < APMIXED_PLL_MAX; i++)
669 clrbits32(plls[i].pwr_reg, PLL_ISO);
670
671 udelay(PLL_ISO_DELAY);
672
673 /* disable glitch free if rate < 374MHz */
674 for (i = 0; i < ARRAY_SIZE(rates); i++) {
675 if (rates[i].rate < 374 * MHz)
676 clrbits32(plls[rates[i].id].reg, GLITCH_FREE_EN);
677 }
678
679 /* disable mfg_ck_en[20], enable mfg_opp_ck_en[2] */
680 clrbits32(&mtk_apmixed->mfgpll_con0, 0x1 << 20);
681 setbits32(&mtk_apmixed->mfgpll_con1, 0x1 << 2);
682
683 /* xPLL Frequency Set */
684 for (i = 0; i < ARRAY_SIZE(rates); i++)
685 pll_set_rate(&plls[rates[i].id], rates[i].rate);
686
687 /* AUDPLL Tuner Frequency Set */
688 write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con3) + 1);
689 write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con3) + 1);
690 write32(&mtk_apmixed->apll3_tuner_con0, read32(&mtk_apmixed->apll3_con3) + 1);
691 write32(&mtk_apmixed->apll4_tuner_con0, read32(&mtk_apmixed->apll4_con3) + 1);
692 write32(&mtk_apmixed->apll5_tuner_con0, read32(&mtk_apmixed->apll5_con3) + 1);
693
694 /* xPLL Frequency Enable */
695 for (i = 0; i < APMIXED_PLL_MAX; i++) {
696 if (i == APMIXED_APLL5)
697 setbits32(plls[i].pwr_reg, MT8195_APLL5_EN);
698 else
699 setbits32(plls[i].reg, MT8195_PLL_EN);
700 }
701
702 /* enable univpll analog divider=13 */
703 setbits32(&mtk_apmixed->univpll_con0, 0x8d);
704
705 /* wait for PLL stable */
706 udelay(PLL_EN_DELAY);
707
708 /* xPLL DIV Enable & RSTB */
709 for (i = 0; i < APMIXED_PLL_MAX; i++) {
710 if (plls[i].rstb_shift != NO_RSTB_SHIFT) {
711 setbits32(plls[i].reg, PLL_DIV_EN);
712 setbits32(plls[i].reg, 1 << plls[i].rstb_shift);
713 }
714 }
715
716 /* MCUCFG CLKMUX */
717 clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1);
718 clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1);
719 clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1);
720
721 clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
722 clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
723 clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
724
725 /* enable infrasys DCM */
726 setbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl, 0x3 << 21);
727 setbits32(&mt8195_infracfg_ao_bcrm->vdnr_dcm_top_infra_ctrl0, 0x2);
728
729 /* dcm_infracfg_ao_aximem_bus_dcm */
730 clrsetbits32(&mt8195_infracfg_ao->infra_aximem_idle_bit_en_0,
731 INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK,
732 INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON);
733 /* dcm_infracfg_ao_infra_bus_dcm */
734 clrsetbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl,
735 INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK,
736 INFRACFG_AO_INFRA_BUS_DCM_REG0_ON);
737 /* dcm_infracfg_ao_infra_rx_p2p_dcm */
738 clrsetbits32(&mt8195_infracfg_ao->p2p_rx_clk_on,
739 INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK,
740 INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON);
741 /* dcm_infracfg_ao_peri_bus_dcm */
742 clrsetbits32(&mt8195_infracfg_ao->peri_bus_dcm_ctrl,
743 INFRACFG_AO_PERI_BUS_DCM_REG0_MASK,
744 INFRACFG_AO_PERI_BUS_DCM_REG0_ON);
745 /* dcm_infracfg_ao_peri_module_dcm */
746 clrsetbits32(&mt8195_infracfg_ao->peri_bus_dcm_ctrl,
747 INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK,
748 INFRACFG_AO_PERI_MODULE_DCM_REG0_ON);
749
750 /* initialize SPM request */
751 setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff);
752
753 /*
754 * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
755 */
756 for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
757 pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
758
759 /* switch sram control to bypass mode for PCIE_MAC_P0 */
760 setbits32(&mtk_spm->ap_mdsrc_req, 0x1);
761
762 /* ctitical clock */
763 write32(&mt8195_infracfg_ao->module_sw_cg_0_clr, 0x00000020);
764 write32(&mt8195_infracfg_ao->module_sw_cg_1_clr, 0x00100000);
765 write32(&mt8195_infracfg_ao->module_sw_cg_2_clr, 0x02000000);
766 write32(&mt8195_infracfg_ao->module_sw_cg_3_clr, 0x00000003);
767
768 /* turn off unused clock */
769 write32(&mt8195_pericfg_ao->peri_module_sw_cg_0_set, 0x10);
770
771 /* scp_dsp for audio */
772 clrbits32(&mt8195_scp_adsp->audiodsp_ck_cg, BIT(0));
773
774 /* audio 26M */
775 setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(4));
776 }
777
778 void mt_pll_raise_little_cpu_freq(u32 freq)
779 {
780 /* switch clock source to intermediate clock */
781 clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M);
782
783 /* disable armpll_ll frequency output */
784 clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8195_PLL_EN);
785
786 /* raise armpll_ll frequency */
787 pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq);
788
789 /* enable armpll_ll frequency output */
790 setbits32(plls[APMIXED_ARMPLL_LL].reg, MT8195_PLL_EN);
791 udelay(PLL_EN_DELAY);
792
793 /* switch clock source back to armpll_ll */
794 clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
795 }
796
797 void mt_pll_raise_cci_freq(u32 freq)
798 {
799 /* switch clock source to intermediate clock */
800 clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M);
801
802 /* disable ccipll frequency output */
803 clrbits32(plls[APMIXED_CCIPLL].reg, MT8195_PLL_EN);
804
805 /* raise ccipll frequency */
806 pll_set_rate(&plls[APMIXED_CCIPLL], freq);
807
808 /* enable ccipll frequency output */
809 setbits32(plls[APMIXED_CCIPLL].reg, MT8195_PLL_EN);
810 udelay(PLL_EN_DELAY);
811
812 /* switch clock source back to ccipll */
813 clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
814 }
815
816 void mt_pll_set_tvd_pll1_freq(u32 freq)
817 {
818 /* disable tvdpll frequency output */
819 clrbits32(plls[APMIXED_TVDPLL1].reg, MT8195_PLL_EN);
820
821 /* set tvdpll frequency */
822 pll_set_rate(&plls[APMIXED_TVDPLL1], freq);
823
824 /* enable tvdpll frequency output */
825 setbits32(plls[APMIXED_TVDPLL1].reg, MT8195_PLL_EN);
826 udelay(PLL_EN_DELAY);
827 }
828
829 void mt_pll_edp_mux_set_sel(u32 sel)
830 {
831 pll_mux_set_sel(&muxes[TOP_EDP_SEL], sel);
832 }
833
834 u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
835 {
836 u32 output, count, clk_dbg_cfg, clk_misc_cfg_0;
837
838 /* backup */
839 clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg);
840 clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0);
841
842 /* set up frequency meter */
843 if (type == FMETER_ABIST) {
844 SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg,
845 CLK_DBG_CFG_ABIST_CK_SEL, id,
846 CLK_DBG_CFG_CKGEN_CK_SEL, 0,
847 CLK_DBG_CFG_METER_CK_SEL, 0,
848 CLK_DBG_CFG_CKGEN_EN, 0);
849 SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
850 CLK_MISC_CFG_0_METER_DIV, 3);
851 } else if (type == FMETER_CKGEN) {
852 SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg,
853 CLK_DBG_CFG_ABIST_CK_SEL, 0,
854 CLK_DBG_CFG_CKGEN_CK_SEL, id,
855 CLK_DBG_CFG_METER_CK_SEL, 1,
856 CLK_DBG_CFG_CKGEN_EN, 1);
857 SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
858 CLK_MISC_CFG_0_METER_DIV, 0);
859 } else {
860 die("unsupported fmeter type\n");
861 }
862
863 /* enable frequency meter */
864 write32(&mtk_topckgen->clk26cali_0, 0x80);
865
866 /* set load count = 1024-1 */
867 SET32_BITFIELDS(&mtk_topckgen->clk26cali_1, CLK26CALI_1_LOAD_CNT, 0x3ff);
868
869 /* trigger frequency meter */
870 SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER, 1);
871
872 /* wait frequency meter until finished */
873 if (wait_us(200, !READ32_BITFIELD(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER))) {
874 count = read32(&mtk_topckgen->clk26cali_1) & 0xffff;
875 output = (count * 26000) / 1024; /* KHz */
876 } else {
877 printk(BIOS_WARNING, "fmeter timeout\n");
878 output = 0;
879 }
880
881 /* disable frequency meter */
882 write32(&mtk_topckgen->clk26cali_0, 0x0000);
883
884 /* restore */
885 write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg);
886 write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0);
887
888 if (type == FMETER_ABIST)
889 return output * 4;
890 else if (type == FMETER_CKGEN)
891 return output;
892
893 return 0;
894 }
895
896 void mt_pll_set_usb_clock(void)
897 {
898 setbits32(&mtk_topckgen->clk_cfg_11_clr, BIT(7) | BIT(15));
899 setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(1) | BIT(31));
900 }
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