src/soc/qualcomm/ipq40xx/blobs_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/cache.h>
   4 #include <device/mmio.h>
   5 #include <cbfs.h>
   6 #include <console/console.h>
   7 #include <string.h>
   8 #include <program_loading.h>
   9 #include <soc/iomap.h>
  10 #include <soc/soc_services.h>
  11
  12 #include "mbn_header.h"
  13
  14 struct cdt_info {
  15         uint32_t        size;           /* size of the whole table */
  16         uint8_t         *cdt_ptr;       /* pointer to CDT */
  17 };
  18
  19 static void *load_ipq_blob(const char *file_name)
  20 {
  21         struct mbn_header *blob_mbn;
  22         void *blob_dest;
  23         size_t blob_size;
  24
  25         blob_mbn = cbfs_map(file_name, &blob_size);
  26         if (!blob_mbn)
  27                 return NULL;
  28
  29         /* some sanity checks on the headers */
  30         if ((blob_mbn->mbn_version != 3) ||
  31             (blob_mbn->mbn_total_size > blob_size))
  32                 return NULL;
  33
  34         blob_dest = (void *)blob_mbn->mbn_destination;
  35
  36         if (blob_mbn->mbn_destination) {
  37                 /* Copy the blob to the appropriate memory location. */
  38                 memcpy(blob_dest, blob_mbn + 1, blob_mbn->mbn_total_size);
  39                 cache_sync_instructions();
  40                 return blob_dest;
  41         }
  42
  43         return blob_mbn;
  44 }
  45
  46 #define DDR_VERSION() ((const char *)"private build")
  47 #define MAX_DDR_VERSION_SIZE 48
  48
  49 typedef struct {
  50         uint64_t        entry_point; /* Write only for Core Boot */
  51         uint32_t        elf_class;
  52 } sys_debug_qsee_info_type_t;
  53
  54 typedef struct {
  55         sys_debug_qsee_info_type_t      *qsee_info;
  56         uint64_t                        sdi_entry; /* Read only for Core Boot */
  57 } sbl_rw_ret_info_t;
  58
  59 sbl_rw_ret_info_t *sbl_rw_ret_info;
  60
  61 int initialize_dram(void)
  62 {
  63         struct mbn_header *cdt;
  64         struct cdt_info cdt_header;
  65         uint32_t sw_entry;
  66         /*
  67          * FIXME: Hard coding the address. Have to somehow get it
  68          * automatically
  69          */
  70         void *tzbsp = (uint8_t *)0x87e80000;
  71
  72         sbl_rw_ret_info_t (*(*ddr_init_function)(struct cdt_info *cdt_header));
  73
  74         cdt = load_ipq_blob(CONFIG_CDT_MBN);
  75         ddr_init_function = load_ipq_blob(CONFIG_DDR_MBN);
  76
  77         if (!cdt || !ddr_init_function) {
  78                 printk(BIOS_ERR, "cdt: %p, ddr_init_function: %p\n",
  79                        cdt, ddr_init_function);
  80                 die("could not find DDR initialization blobs\n");
  81         }
  82
  83         cdt_header.size = cdt->mbn_total_size;
  84         cdt_header.cdt_ptr = (uint8_t *)(cdt + 1);
  85
  86         sbl_rw_ret_info = ddr_init_function(&cdt_header);
  87         if (sbl_rw_ret_info == NULL)
  88                 die("Fail to Initialize DDR\n");
  89
  90         /*
  91          * Once DDR initializer finished, its version can be found at a fixed
  92          * address in SRAM.
  93          */
  94         printk(BIOS_INFO, "DDR version %.*s initialized\n",
  95                MAX_DDR_VERSION_SIZE, DDR_VERSION());
  96
  97         printk(BIOS_INFO, "SDI Entry: 0x%llx\n", sbl_rw_ret_info->sdi_entry);
  98         sw_entry = read32(TCSR_RESET_DEBUG_SW_ENTRY) & 0x1;
  99         sw_entry |= (sbl_rw_ret_info->sdi_entry & ~0x1);
 100         write32(TCSR_RESET_DEBUG_SW_ENTRY, sw_entry);
 101         sbl_rw_ret_info->qsee_info->entry_point = (uint32_t)tzbsp;
 102
 103         return 0;
 104 }
 105
 106 void start_tzbsp(void)
 107 {
 108         void *tzbsp = load_ipq_blob(CONFIG_TZ_MBN);
 109
 110         if (!tzbsp)
 111                 die("could not find or map TZBSP\n");
 112
 113         printk(BIOS_INFO, "Starting TZBSP\n");
 114
 115         tz_init_wrapper(0, 0, tzbsp);
 116 }