mb/system76/cml-u/dt: Make use of chipset devicetree
[coreboot.git] / src / soc / qualcomm / ipq806x / blobs_init.c
blob851ee814d4ed9f4e6cf6478c6b6dad213540e2b7
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <arch/cache.h>
4 #include <device/mmio.h>
5 #include <cbfs.h>
6 #include <console/console.h>
7 #include <string.h>
8 #include <timer.h>
10 #include <soc/iomap.h>
11 #include <soc/soc_services.h>
13 #include "mbn_header.h"
15 static void *load_ipq_blob(const char *file_name)
17 struct mbn_header *blob_mbn;
18 void *blob_dest;
19 size_t blob_size;
21 blob_mbn = cbfs_map(file_name, &blob_size);
22 if (!blob_mbn)
23 return NULL;
25 /* some sanity checks on the headers */
26 if ((blob_mbn->mbn_version != 3) ||
27 (blob_mbn->mbn_total_size > blob_size))
28 return NULL;
30 blob_dest = (void *)blob_mbn->mbn_destination;
31 if (blob_mbn->mbn_destination) {
32 /* Copy the blob to the appropriate memory location. */
33 memcpy(blob_dest, blob_mbn + 1, blob_mbn->mbn_total_size);
34 cache_sync_instructions();
35 return blob_dest;
39 * The blob did not have to be relocated, return its address in CBFS
40 * cache.
42 return blob_mbn + 1;
45 #define DDR_VERSION() ((const char *)0x2a03f600)
46 #define MAX_DDR_VERSION_SIZE 48
48 int initialize_dram(void)
50 void *cdt;
51 int (*ddr_init_function)(void *cdt_header);
53 cdt = load_ipq_blob("cdt.mbn");
54 ddr_init_function = load_ipq_blob("ddr.mbn");
56 if (!cdt || !ddr_init_function) {
57 printk(BIOS_ERR, "cdt: %p, ddr_init_function: %p\n",
58 cdt, ddr_init_function);
59 die("could not find DDR initialization blobs\n");
62 if (ddr_init_function(cdt) < 0)
63 die("Fail to Initialize DDR\n");
66 * Once DDR initializer finished, its version can be found at a fixed
67 * address in SRAM.
69 printk(BIOS_INFO, "DDR version %.*s initialized\n",
70 MAX_DDR_VERSION_SIZE, DDR_VERSION());
72 return 0;
75 void start_tzbsp(void)
77 void *tzbsp = load_ipq_blob("tz.mbn");
79 if (!tzbsp)
80 die("could not find or map TZBSP\n");
82 printk(BIOS_INFO, "Starting TZBSP\n");
84 tz_init_wrapper(0, 0, tzbsp);
87 /* RPM version is encoded in a 32 bit word at the fixed address */
88 #define RPM_VERSION() (*((u32 *)(0x00108008)))
89 void start_rpm(void)
91 u32 load_addr;
92 u32 ready_mask = 1 << 10;
93 u32 rpm_version;
95 struct stopwatch sw;
97 if (read32(RPM_SIGNAL_COOKIE) == RPM_FW_MAGIC_NUM) {
98 printk(BIOS_INFO, "RPM appears to have already started\n");
99 return;
102 load_addr = (u32)load_ipq_blob("rpm.mbn");
103 if (!load_addr)
104 die("could not find or map RPM code\n");
106 printk(BIOS_INFO, "Starting RPM\n");
108 /* Clear 'ready' indication. */
110 * RPM_INT_ACK is clear-on-write type register,
111 * read-modify-write is not recommended.
113 write32(RPM_INT_ACK, ready_mask);
115 /* Set RPM entry address */
116 write32(RPM_SIGNAL_ENTRY, load_addr);
117 /* Set cookie */
118 write32(RPM_SIGNAL_COOKIE, RPM_FW_MAGIC_NUM);
120 /* Wait for RPM start indication, up to 100ms. */
121 stopwatch_init_usecs_expire(&sw, 100000);
122 while (!(read32(RPM_INT) & ready_mask))
123 if (stopwatch_expired(&sw))
124 die("RPM Initialization failed\n");
126 /* Acknowledge RPM initialization */
127 write32(RPM_INT_ACK, ready_mask);
129 /* Report RPM version, it is encoded in a 32 bit value. */
130 rpm_version = RPM_VERSION();
131 printk(BIOS_INFO, "Started RPM version %d.%d.%d\n",
132 rpm_version >> 24,
133 (rpm_version >> 16) & 0xff,
134 rpm_version & 0xffff);