src/soc/qualcomm/qcs405/memlayout.ld

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <memlayout.h>
   4 #include <arch/header.ld>
   5
   6 /* SYSTEM_IMEM : 0x8600000 - 0x8607FFF */
   7 #define SSRAM_START(addr) REGION_START(ssram, addr)
   8 #define SSRAM_END(addr) REGION_END(ssram, addr)
   9
  10 /* BOOT_IMEM   : 0x8C00000 - 0x8D80000 */
  11 #define BSRAM_START(addr) REGION_START(bsram, addr)
  12 #define BSRAM_END(addr) REGION_END(bsram, addr)
  13
  14 SECTIONS
  15 {
  16         SSRAM_START(0x8600000)
  17         SSRAM_END(0x8608000)
  18
  19         BSRAM_START(0x8C00000)
  20         OVERLAP_VERSTAGE_ROMSTAGE(0x8C00000, 100K)
  21         REGION(fw_reserved2, 0x8C19000, 0x16000, 4096)
  22         BOOTBLOCK(0x8C2F000, 40K)
  23         TTB(0x8C39000, 56K)
  24         VBOOT2_WORK(0x8C47000, 12K)
  25         STACK(0x8C4B000, 16K)
  26         TIMESTAMP(0x8C4F000, 1K)
  27         PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K)
  28         PRERAM_CBFS_CACHE(0x8C57400, 62K)
  29         CBFS_MCACHE(0x8C66C00, 8K)
  30         FMAP_CACHE(0x8C68C00, 2K)
  31         REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100)
  32         BSRAM_END(0x8D80000)
  33
  34         DRAM_START(0x80000000)
  35         /* DDR Carveout for BL31 usage */
  36         REGION(dram_reserved, 0x85000000, 0x5100000, 4096)
  37         POSTRAM_CBFS_CACHE(0x9F800000, 384K)
  38         RAMSTAGE(0x9F860000, 2M)
  39 }