src/soc/qualcomm/qcs405/spi.c

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2
   3 #include <device/mmio.h>
   4 #include <console/console.h>
   5 #include <delay.h>
   6 #include <gpio.h>
   7 #include <soc/iomap.h>
   8 #include <soc/spi.h>
   9 #include <soc/clock.h>
  10 #include <spi_flash.h>
  11 #include <timer.h>
  12
  13 static const struct blsp_spi spi_reg[] = {
  14         /* BLSP0 registers for SPI interface */
  15         {
  16                 BLSP0_SPI_CONFIG_REG,
  17                 BLSP0_SPI_IO_CONTROL_REG,
  18                 BLSP0_SPI_ERROR_FLAGS_REG,
  19                 BLSP0_SPI_ERROR_FLAGS_EN_REG,
  20                 BLSP0_QUP_CONFIG_REG,
  21                 BLSP0_QUP_ERROR_FLAGS_REG,
  22                 BLSP0_QUP_ERROR_FLAGS_EN_REG,
  23                 BLSP0_QUP_OPERATIONAL_REG,
  24                 BLSP0_QUP_IO_MODES_REG,
  25                 BLSP0_QUP_STATE_REG,
  26                 BLSP0_QUP_INPUT_FIFOc_REG(0),
  27                 BLSP0_QUP_OUTPUT_FIFOc_REG(0),
  28                 BLSP0_QUP_MX_INPUT_COUNT_REG,
  29                 BLSP0_QUP_MX_OUTPUT_COUNT_REG,
  30                 BLSP0_QUP_SW_RESET_REG,
  31                 0,
  32                 0,
  33                 BLSP0_QUP_OPERATIONAL_MASK,
  34                 BLSP0_SPI_DEASSERT_WAIT_REG,
  35         },
  36         {0}, {0}, {0},
  37         /* BLSP4 registers for SPI interface */
  38         {
  39                 BLSP4_SPI_CONFIG_REG,
  40                 BLSP4_SPI_IO_CONTROL_REG,
  41                 BLSP4_SPI_ERROR_FLAGS_REG,
  42                 BLSP4_SPI_ERROR_FLAGS_EN_REG,
  43                 BLSP4_QUP_CONFIG_REG,
  44                 BLSP4_QUP_ERROR_FLAGS_REG,
  45                 BLSP4_QUP_ERROR_FLAGS_EN_REG,
  46                 BLSP4_QUP_OPERATIONAL_REG,
  47                 BLSP4_QUP_IO_MODES_REG,
  48                 BLSP4_QUP_STATE_REG,
  49                 BLSP4_QUP_INPUT_FIFOc_REG(0),
  50                 BLSP4_QUP_OUTPUT_FIFOc_REG(0),
  51                 BLSP4_QUP_MX_INPUT_COUNT_REG,
  52                 BLSP4_QUP_MX_OUTPUT_COUNT_REG,
  53                 BLSP4_QUP_SW_RESET_REG,
  54                 0,
  55                 0,
  56                 BLSP4_QUP_OPERATIONAL_MASK,
  57                 BLSP4_SPI_DEASSERT_WAIT_REG,
  58         },
  59         /* BLSP5 registers for SPI interface */
  60         {
  61                 BLSP5_SPI_CONFIG_REG,
  62                 BLSP5_SPI_IO_CONTROL_REG,
  63                 BLSP5_SPI_ERROR_FLAGS_REG,
  64                 BLSP5_SPI_ERROR_FLAGS_EN_REG,
  65                 BLSP5_QUP_CONFIG_REG,
  66                 BLSP5_QUP_ERROR_FLAGS_REG,
  67                 BLSP5_QUP_ERROR_FLAGS_EN_REG,
  68                 BLSP5_QUP_OPERATIONAL_REG,
  69                 BLSP5_QUP_IO_MODES_REG,
  70                 BLSP5_QUP_STATE_REG,
  71                 BLSP5_QUP_INPUT_FIFOc_REG(0),
  72                 BLSP5_QUP_OUTPUT_FIFOc_REG(0),
  73                 BLSP5_QUP_MX_INPUT_COUNT_REG,
  74                 BLSP5_QUP_MX_OUTPUT_COUNT_REG,
  75                 BLSP5_QUP_SW_RESET_REG,
  76                 0,
  77                 0,
  78                 BLSP5_QUP_OPERATIONAL_MASK,
  79                 BLSP5_SPI_DEASSERT_WAIT_REG,
  80         },
  81 };
  82
  83 static int check_bit_state(void *reg_addr, int mask,
  84                                 int val, int us_delay)
  85 {
  86         unsigned int count = TIMEOUT_CNT;
  87
  88         while ((read32(reg_addr) & mask) != val) {
  89                 count--;
  90                 if (count == 0)
  91                         return -ETIMEDOUT;
  92                 udelay(us_delay);
  93         }
  94
  95         return SUCCESS;
  96 }
  97
  98 /*
  99  * Check whether QUPn State is valid
 100  */
 101 static int check_qup_state_valid(struct qcs_spi_slave *ds)
 102 {
 103         return check_bit_state(ds->regs->qup_state, QUP_STATE_VALID_MASK,
 104                                 QUP_STATE_VALID, 1);
 105 }
 106
 107 /*
 108  * Configure QUPn Core state
 109  */
 110 static int config_spi_state(struct qcs_spi_slave *ds, unsigned int state)
 111 {
 112         uint32_t val;
 113         int ret = SUCCESS;
 114
 115         ret = check_qup_state_valid(ds);
 116         if (ret != SUCCESS)
 117                 return ret;
 118
 119         switch (state) {
 120         case QUP_STATE_RUN:
 121                 /* Set the state to RUN */
 122                 val = ((read32(ds->regs->qup_state) & ~QUP_STATE_MASK)
 123                                 | QUP_STATE_RUN);
 124                 write32(ds->regs->qup_state, val);
 125                 ret = check_qup_state_valid(ds);
 126                 break;
 127         case QUP_STATE_RESET:
 128                 /* Set the state to RESET */
 129                 val = ((read32(ds->regs->qup_state) & ~QUP_STATE_MASK)
 130                                 | QUP_STATE_RESET);
 131                 write32(ds->regs->qup_state, val);
 132                 ret = check_qup_state_valid(ds);
 133                 break;
 134         default:
 135                 printk(BIOS_ERR, "unsupported QUP SPI state : %d\n", state);
 136                 ret = -EINVAL;
 137                 break;
 138         }
 139
 140         return ret;
 141 }
 142
 143 /*
 144  * Set QUPn SPI Mode
 145  */
 146 static void spi_set_mode(struct qcs_spi_slave *ds, unsigned int mode)
 147 {
 148         unsigned int clk_idle_state;
 149         unsigned int input_first_mode;
 150         uint32_t val;
 151
 152         switch (mode) {
 153         case SPI_MODE0:
 154                 clk_idle_state = 0;
 155                 input_first_mode = SPI_CONFIG_INPUT_FIRST;
 156                 break;
 157         case SPI_MODE1:
 158                 clk_idle_state = 0;
 159                 input_first_mode = 0;
 160                 break;
 161         case SPI_MODE2:
 162                 clk_idle_state = 1;
 163                 input_first_mode = SPI_CONFIG_INPUT_FIRST;
 164                 break;
 165         case SPI_MODE3:
 166                 clk_idle_state = 1;
 167                 input_first_mode = 0;
 168                 break;
 169         default:
 170                 printk(BIOS_ERR, "unsupported spi mode : %d\n", mode);
 171                 return;
 172         }
 173
 174         val = read32(ds->regs->spi_config);
 175         val |= input_first_mode;
 176         write32(ds->regs->spi_config, val);
 177         val = read32(ds->regs->io_control);
 178
 179         if (clk_idle_state)
 180                 val |= SPI_IO_CTRL_CLOCK_IDLE_HIGH;
 181         else
 182                 val &= ~SPI_IO_CTRL_CLOCK_IDLE_HIGH;
 183
 184         write32(ds->regs->io_control, val);
 185 }
 186
 187 /*
 188  * Reset entire QUP and all mini cores
 189  */
 190 static void spi_reset(struct qcs_spi_slave *ds)
 191 {
 192         write32(ds->regs->qup_sw_reset, 0x1);
 193         udelay(5);
 194         check_qup_state_valid(ds);
 195 }
 196
 197 static struct qcs_spi_slave spi_slave_pool[3];
 198
 199 static struct qcs_spi_slave *to_qcs_spi(const struct spi_slave *slave)
 200 {
 201         struct qcs_spi_slave *ds;
 202         size_t i;
 203
 204         for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) {
 205                 ds = spi_slave_pool + i;
 206
 207                 if (!ds->allocated)
 208                         continue;
 209
 210                 if ((ds->slave.bus == slave->bus) &&
 211                     (ds->slave.cs == slave->cs))
 212                         return ds;
 213         }
 214
 215         return NULL;
 216 }
 217
 218 static void write_force_cs(const struct spi_slave *slave, int assert)
 219 {
 220         struct qcs_spi_slave *ds = to_qcs_spi(slave);
 221         if (assert)
 222                 clrsetbits32(ds->regs->io_control,
 223                         SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN);
 224         else
 225                 clrsetbits32(ds->regs->io_control,
 226                         SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS);
 227 }
 228
 229 /*
 230  * BLSP QUPn SPI Hardware Initialisation
 231  */
 232 static int spi_hw_init(struct qcs_spi_slave *ds)
 233 {
 234         int ret;
 235
 236         ds->initialized = 0;
 237
 238         /* QUPn module configuration */
 239         spi_reset(ds);
 240
 241         /* Set the QUPn state */
 242         ret = config_spi_state(ds, QUP_STATE_RESET);
 243         if (ret)
 244                 return ret;
 245
 246         /*
 247          * Configure Mini core to SPI core with Input Output enabled,
 248          * SPI master, N = 8 bits
 249          */
 250         clrsetbits32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK |
 251                                                 QUP_CONF_INPUT_MSK |
 252                                                 QUP_CONF_OUTPUT_MSK |
 253                                                 QUP_CONF_N_MASK,
 254                                                 QUP_CONFIG_MINI_CORE_SPI |
 255                                                 QUP_CONF_INPUT_ENA |
 256                                                 QUP_CONF_OUTPUT_ENA |
 257                                                 QUP_CONF_N_SPI_8_BIT_WORD);
 258
 259         /*
 260          * Configure Input first SPI protocol,
 261          * SPI master mode and no loopback
 262          */
 263         clrsetbits32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK |
 264                                                 SPI_CONFIG_NO_SLAVE_OPER_MSK,
 265                                                 SPI_CONFIG_NO_LOOP_BACK |
 266                                                 SPI_CONFIG_NO_SLAVE_OPER);
 267
 268         /*
 269          * Configure SPI IO Control Register
 270          * CLK_ALWAYS_ON = 0
 271          * MX_CS_MODE = 0
 272          * NO_TRI_STATE = 1
 273          */
 274         write32(ds->regs->io_control, SPI_IO_CTRL_CLK_ALWAYS_ON |
 275                 SPI_IO_CTRL_NO_TRI_STATE | SPI_IO_CTRL_MX_CS_MODE);
 276
 277         /*
 278          * Configure SPI IO Modes.
 279          * OUTPUT_BIT_SHIFT_EN = 1
 280          * INPUT_MODE = Block Mode
 281          * OUTPUT MODE = Block Mode
 282          */
 283         clrsetbits32(ds->regs->qup_io_modes,
 284                                 QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK |
 285                                 QUP_IO_MODES_INPUT_MODE_MSK |
 286                                 QUP_IO_MODES_OUTPUT_MODE_MSK,
 287                                 QUP_IO_MODES_OUTPUT_BIT_SHIFT_EN |
 288                                 QUP_IO_MODES_INPUT_BLOCK_MODE |
 289                                 QUP_IO_MODES_OUTPUT_BLOCK_MODE);
 290
 291         spi_set_mode(ds, ds->mode);
 292
 293         /* Disable Error mask */
 294         write32(ds->regs->error_flags_en, 0);
 295         write32(ds->regs->qup_error_flags_en, 0);
 296         write32(ds->regs->qup_deassert_wait, 0);
 297
 298         ds->initialized = 1;
 299
 300         return SUCCESS;
 301 }
 302
 303 static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
 304 {
 305         struct qcs_spi_slave *ds = to_qcs_spi(slave);
 306         unsigned int ret;
 307
 308         ret = spi_hw_init(ds);
 309         if (ret)
 310                 return -EIO;
 311         switch (slave->bus) {
 312         case 4:
 313                 gpio_configure
 314                 (GPIO(37), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); // MOSI
 315                 gpio_configure
 316                 (GPIO(38), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); // MISO
 317                 gpio_configure
 318                 (GPIO(117), 2, GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT); // CS
 319                 gpio_configure
 320                 (GPIO(118), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT);// CLK
 321                 break;
 322         case 5:
 323                 gpio_configure
 324                 (GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI
 325                 gpio_configure
 326                 (GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO
 327                 gpio_configure
 328                 (GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS
 329                 gpio_configure
 330                 (GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK
 331                 break;
 332         default:
 333                 printk(BIOS_ERR, "SPI error: unsupported bus %d "
 334                         "(Supported buses 0, 1, 2, 3, 4, 5)\n", slave->bus);
 335                 break;
 336         }
 337         write_force_cs(slave, 1);
 338
 339         return SUCCESS;
 340 }
 341
 342 static void spi_ctrlr_release_bus(const struct spi_slave *slave)
 343 {
 344         struct qcs_spi_slave *ds = to_qcs_spi(slave);
 345
 346         /* Reset the SPI hardware */
 347         write_force_cs(slave, 0);
 348         spi_reset(ds);
 349         ds->initialized = 0;
 350 }
 351
 352 /*
 353  * Function to write data to OUTPUT FIFO
 354  */
 355 static void spi_write_byte(struct qcs_spi_slave *ds, unsigned char data)
 356 {
 357         /* Wait for space in the FIFO */
 358         while ((read32(ds->regs->qup_operational) & OUTPUT_FIFO_FULL))
 359                 udelay(1);
 360
 361         /* Write the byte of data */
 362         write32(ds->regs->qup_output_fifo, data);
 363 }
 364
 365 /*
 366  * Function to read data from Input FIFO
 367  */
 368 static unsigned char spi_read_byte(struct qcs_spi_slave *ds)
 369 {
 370         /* Wait for Data in FIFO */
 371         while (!(read32(ds->regs->qup_operational) & INPUT_FIFO_NOT_EMPTY))
 372                 udelay(1);
 373
 374         /* Read a byte of data */
 375         return read32(ds->regs->qup_input_fifo) & 0xff;
 376 }
 377
 378 /*
 379  * Function to check whether Input or Output FIFO
 380  * has data to be serviced
 381  */
 382 static int check_fifo_status(void *reg_addr)
 383 {
 384         unsigned int count = TIMEOUT_CNT;
 385         unsigned int status_flag;
 386         unsigned int val;
 387
 388         do {
 389                 val = read32(reg_addr);
 390                 count--;
 391                 if (count == 0)
 392                         return -ETIMEDOUT;
 393                 status_flag = ((val & OUTPUT_SERVICE_FLAG) |
 394                                         (val & INPUT_SERVICE_FLAG));
 395         } while (!status_flag);
 396
 397         return SUCCESS;
 398 }
 399
 400 /*
 401  * Function to configure Input and Output enable/disable
 402  */
 403 static void enable_io_config(struct qcs_spi_slave *ds,
 404                                 uint32_t write_cnt, uint32_t read_cnt)
 405 {
 406         if (write_cnt) {
 407                 clrsetbits32(ds->regs->qup_config,
 408                                 QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
 409         } else {
 410                 clrsetbits32(ds->regs->qup_config,
 411                                 QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT);
 412         }
 413
 414         if (read_cnt) {
 415                 clrsetbits32(ds->regs->qup_config,
 416                                 QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA);
 417         } else {
 418                 clrsetbits32(ds->regs->qup_config,
 419                                 QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
 420         }
 421 }
 422
 423 /*
 424  * Function to read bytes number of data from the Input FIFO
 425  */
 426 static int __blsp_spi_read(struct qcs_spi_slave *ds, u8 *data_buffer,
 427                                 unsigned int bytes)
 428 {
 429         uint32_t val;
 430         unsigned int i;
 431         unsigned int fifo_count;
 432         int ret = SUCCESS;
 433         int state_config;
 434         struct stopwatch sw;
 435
 436         /* Configure no of bytes to read */
 437         state_config = config_spi_state(ds, QUP_STATE_RESET);
 438         if (state_config)
 439                 return state_config;
 440
 441         /* Configure input and output enable */
 442         enable_io_config(ds, 0, bytes);
 443
 444         write32(ds->regs->qup_mx_input_count, bytes);
 445
 446         state_config = config_spi_state(ds, QUP_STATE_RUN);
 447         if (state_config)
 448                 return state_config;
 449
 450         while (bytes) {
 451                 ret = check_fifo_status(ds->regs->qup_operational);
 452                 if (ret != SUCCESS)
 453                         goto out;
 454
 455                 val = read32(ds->regs->qup_operational);
 456                 if (val & INPUT_SERVICE_FLAG) {
 457                         /*
 458                          * acknowledge to hw that software will
 459                          * read input data
 460                          */
 461                         val &= INPUT_SERVICE_FLAG;
 462                         write32(ds->regs->qup_operational, val);
 463
 464                         fifo_count = ((bytes > SPI_INPUT_BLOCK_SIZE) ?
 465                                         SPI_INPUT_BLOCK_SIZE : bytes);
 466
 467                         for (i = 0; i < fifo_count; i++) {
 468                                 *data_buffer = spi_read_byte(ds);
 469                                 data_buffer++;
 470                                 bytes--;
 471                         }
 472                 }
 473         }
 474
 475         stopwatch_init_msecs_expire(&sw, 10);
 476
 477         do {
 478                 val = read32(ds->regs->qup_operational);
 479                 if (stopwatch_expired(&sw)) {
 480                         printk(BIOS_ERR, "SPI FIFO read timeout\n");
 481                         ret = -ETIMEDOUT;
 482                         goto out;
 483                 }
 484         } while (!(val & MAX_INPUT_DONE_FLAG));
 485
 486 out:
 487         /*
 488          * Put the SPI Core back in the Reset State
 489          * to end the transfer
 490          */
 491         (void)config_spi_state(ds, QUP_STATE_RESET);
 492         return ret;
 493 }
 494
 495 static int blsp_spi_read(struct qcs_spi_slave *ds, u8 *data_buffer,
 496                                 unsigned int bytes)
 497 {
 498         int length, ret;
 499
 500         while (bytes) {
 501                 length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
 502
 503                 ret = __blsp_spi_read(ds, data_buffer, length);
 504                 if (ret != SUCCESS)
 505                         return ret;
 506
 507                 data_buffer += length;
 508                 bytes -= length;
 509         }
 510
 511         return 0;
 512 }
 513
 514 /*
 515  * Function to write data to the Output FIFO
 516  */
 517 static int __blsp_spi_write(struct qcs_spi_slave *ds, const u8 *cmd_buffer,
 518                                 unsigned int bytes)
 519 {
 520         uint32_t val;
 521         unsigned int i;
 522         unsigned int write_len = bytes;
 523         unsigned int read_len = bytes;
 524         unsigned int fifo_count;
 525         int ret = SUCCESS;
 526         int state_config;
 527         struct stopwatch sw;
 528
 529         state_config = config_spi_state(ds, QUP_STATE_RESET);
 530         if (state_config)
 531                 return state_config;
 532
 533         /* Configure input and output enable */
 534         enable_io_config(ds, write_len, read_len);
 535         /* No of bytes to be written in Output FIFO */
 536         write32(ds->regs->qup_mx_output_count, bytes);
 537         write32(ds->regs->qup_mx_input_count, bytes);
 538         state_config = config_spi_state(ds, QUP_STATE_RUN);
 539
 540         if (state_config)
 541                 return state_config;
 542
 543         /*
 544          * read_len considered to ensure that we read the dummy data for the
 545          * write we performed. This is needed to ensure with WR-RD transaction
 546          * to get the actual data on the subsequent read cycle that happens
 547          */
 548         while (write_len || read_len) {
 549                 ret = check_fifo_status(ds->regs->qup_operational);
 550                 if (ret != SUCCESS)
 551                         goto out;
 552
 553                 val = read32(ds->regs->qup_operational);
 554                 if (val & OUTPUT_SERVICE_FLAG) {
 555                         /*
 556                          * acknowledge to hw that software will write
 557                          * expected output data
 558                          */
 559                         val &= OUTPUT_SERVICE_FLAG;
 560                         write32(ds->regs->qup_operational, val);
 561
 562                         if (write_len > SPI_OUTPUT_BLOCK_SIZE)
 563                                 fifo_count = SPI_OUTPUT_BLOCK_SIZE;
 564                         else
 565                                 fifo_count = write_len;
 566
 567                         for (i = 0; i < fifo_count; i++) {
 568                                 /* Write actual data to output FIFO */
 569                                 spi_write_byte(ds, *cmd_buffer);
 570                                 cmd_buffer++;
 571                                 write_len--;
 572                         }
 573                 }
 574
 575                 if (val & INPUT_SERVICE_FLAG) {
 576                         /*
 577                          * acknowledge to hw that software
 578                          * will read input data
 579                          */
 580                         val &= INPUT_SERVICE_FLAG;
 581                         write32(ds->regs->qup_operational, val);
 582
 583                         if (read_len > SPI_INPUT_BLOCK_SIZE)
 584                                 fifo_count = SPI_INPUT_BLOCK_SIZE;
 585                         else
 586                                 fifo_count = read_len;
 587
 588                         for (i = 0; i < fifo_count; i++) {
 589                                 /* Read dummy data for the data written */
 590                                 (void)spi_read_byte(ds);
 591
 592                                 /* Decrement the read count after reading the
 593                                  * dummy data from the device. This is to make
 594                                  * sure we read dummy data before we write the
 595                                  * data to fifo
 596                                  */
 597                                 read_len--;
 598                         }
 599                 }
 600         }
 601
 602         stopwatch_init_msecs_expire(&sw, 10);
 603
 604         do {
 605                 val = read32(ds->regs->qup_operational);
 606                 if (stopwatch_expired(&sw)) {
 607                         printk(BIOS_ERR, "SPI FIFO write timeout\n");
 608                         ret = -ETIMEDOUT;
 609                         goto out;
 610                 }
 611
 612         } while (!(val & MAX_OUTPUT_DONE_FLAG));
 613
 614 out:
 615         /*
 616          * Put the SPI Core back in the Reset State
 617          * to end the transfer
 618          */
 619         (void)config_spi_state(ds, QUP_STATE_RESET);
 620
 621         return ret;
 622 }
 623
 624 static int blsp_spi_write(struct qcs_spi_slave *ds, u8 *cmd_buffer,
 625                                 unsigned int bytes)
 626 {
 627         int length, ret;
 628
 629         while (bytes) {
 630                 length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
 631
 632                 ret = __blsp_spi_write(ds, cmd_buffer, length);
 633                 if (ret != SUCCESS) {
 634                         printk(BIOS_ERR, "SPI:DBG write not success\n");
 635                         return ret;
 636                 }
 637
 638                 cmd_buffer += length;
 639                 bytes -= length;
 640         }
 641
 642         return 0;
 643 }
 644
 645 /*
 646  * This function is invoked with either tx_buf or rx_buf.
 647  * Calling this function with both null does a chip select change.
 648  */
 649 static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 650                         size_t out_bytes, void *din, size_t in_bytes)
 651 {
 652         struct qcs_spi_slave *ds = to_qcs_spi(slave);
 653         u8 *txp = (u8 *)dout;
 654         u8 *rxp = (u8 *)din;
 655         int ret;
 656
 657         ret = config_spi_state(ds, QUP_STATE_RESET);
 658         if (ret != SUCCESS)
 659                 return ret;
 660
 661         if (dout != NULL) {
 662                 ret = blsp_spi_write(ds, txp, (unsigned int)out_bytes);
 663                 if (ret != SUCCESS)
 664                         goto out;
 665         }
 666
 667         if (din != NULL) {
 668                 ret = blsp_spi_read(ds, rxp, in_bytes);
 669                 if (ret != SUCCESS)
 670                         goto out;
 671         }
 672
 673 out:
 674         /*
 675          * Put the SPI Core back in the Reset State
 676          * to end the transfer
 677          */
 678         (void)config_spi_state(ds, QUP_STATE_RESET);
 679
 680         return ret;
 681 }
 682
 683 static int spi_ctrlr_setup(const struct spi_slave *slave)
 684 {
 685         struct qcs_spi_slave *ds = NULL;
 686         int i;
 687         unsigned int bus = slave->bus;
 688         unsigned int cs = slave->cs;
 689         int qup = 0;
 690         int blsp = 2;
 691
 692         if (((bus != BLSP4_SPI) && (bus != BLSP5_SPI)) || cs != 0) {
 693                 printk(BIOS_ERR,
 694                         "SPI error: unsupported bus %d or cs %d\n", bus, cs);
 695                 return -1;
 696         }
 697
 698         for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) {
 699                 if (spi_slave_pool[i].allocated)
 700                         continue;
 701                 ds = spi_slave_pool + i;
 702                 ds->slave.bus = bus;
 703                 ds->slave.cs = cs;
 704                 ds->regs = &spi_reg[bus];
 705                 ds->mode = SPI_MODE0;
 706                 ds->freq = 50000000;
 707
 708                 if (bus == BLSP4_SPI) {
 709                         ds->freq = 1000000;
 710                         qup = 4;
 711                         blsp = 1;
 712                 }
 713
 714                 clock_configure_spi(blsp, qup, ds->freq);
 715                 clock_enable_spi(blsp, qup);
 716
 717                 ds->allocated = 1;
 718
 719                 return 0;
 720         }
 721
 722         printk(BIOS_ERR, "SPI error: all %d pools busy\n", i);
 723         return -1;
 724 }
 725
 726 static int xfer_vectors(const struct spi_slave *slave,
 727                         struct spi_op vectors[], size_t count)
 728 {
 729         return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer);
 730 }
 731
 732 static const struct spi_ctrlr spi_ctrlr = {
 733         .setup = spi_ctrlr_setup,
 734         .claim_bus = spi_ctrlr_claim_bus,
 735         .release_bus = spi_ctrlr_release_bus,
 736         .xfer = spi_ctrlr_xfer,
 737         .xfer_vector = xfer_vectors,
 738         .max_xfer_size = MAX_PACKET_COUNT,
 739 };
 740
 741 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 742         {
 743                 .ctrlr = &spi_ctrlr,
 744                 .bus_start = BLSP5_SPI,
 745                 .bus_end = BLSP5_SPI,
 746         },
 747         {
 748                 .ctrlr = &spi_ctrlr,
 749                 .bus_start = BLSP4_SPI,
 750                 .bus_end = BLSP4_SPI,
 751         },
 752 };
 753
 754 const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);