src/soc/qualcomm/qcs405/usb.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <console/console.h>
   5 #include <delay.h>
   6 #include <soc/usb.h>
   7 #include <soc/clock.h>
   8 #include <types.h>
   9
  10 /* USB BASE ADDRESS */
  11 #define USB_HOST0_DWC3_BASE             0x758C100
  12 #define USB3_USB30_QSCRATCH_BASE        0x7678800
  13 #define USB2_FEMTO_PHY_PRI_BASE         0x007A000
  14 #define USB_HOST1_DWC3_BASE             0x78CC100
  15 #define USB2_USB30_QSCRATCH_BASE        0x79B8800
  16 #define USB2_FEMTO_PHY_SEC_BASE         0x007C000
  17
  18 struct usb_qscratch {
  19         u8 rsvd0[8];
  20         u32 *qscratch_cfg_reg;
  21
  22 };
  23 check_member(usb_qscratch, qscratch_cfg_reg, 0x08);
  24
  25 struct usb_usb2_phy_dig {
  26         u8 rsvd1[116];
  27         u32 utmi_ctrl5;
  28         u32 ctrl_common0;
  29         u32 ctrl_common1;
  30         u8 rsvd2[12];
  31         u32 phy_ctrl1;
  32         u32 phy_ctrl2;
  33         u8 rsvd3;
  34         u32 override_x0;
  35         u32 override_x1;
  36         u32 override_x2;
  37         u32 override_x3;
  38         u8 rsvd4[24];
  39         u32 tcsr_ctrl;
  40         u8 rsvd5[36];
  41         u32 refclk_ctrl;
  42 };
  43 check_member(usb_usb2_phy_dig, utmi_ctrl5, 0x74);
  44 check_member(usb_usb2_phy_dig, phy_ctrl1, 0x8C);
  45 check_member(usb_usb2_phy_dig, override_x0, 0x98);
  46 check_member(usb_usb2_phy_dig, tcsr_ctrl, 0xC0);
  47 check_member(usb_usb2_phy_dig, refclk_ctrl, 0xE8);
  48
  49 struct usb_dwc3 {
  50         u32 sbuscfg0;
  51         u32 sbuscfg1;
  52         u32 txthrcfg;
  53         u32 rxthrcfg;
  54         u32 ctl;
  55         u32 pmsts;
  56         u32 sts;
  57         u32 uctl1;
  58         u32 snpsid;
  59         u32 gpio;
  60         u32 uid;
  61         u32 uctl;
  62         u64 buserraddr;
  63         u64 prtbimap;
  64         u8 reserved1[32];
  65         u32 dbgfifospace;
  66         u32 dbgltssm;
  67         u32 dbglnmcc;
  68         u32 dbgbmu;
  69         u32 dbglspmux;
  70         u32 dbglsp;
  71         u32 dbgepinfo0;
  72         u32 dbgepinfo1;
  73         u64 prtbimap_hs;
  74         u64 prtbimap_fs;
  75         u8 reserved2[112];
  76         u32 usb2phycfg;
  77         u8 reserved3[60];
  78         u32 usb2i2cctl;
  79         u8 reserved4[60];
  80         u32 usb2phyacc;
  81         u8 reserved5[60];
  82         u32 usb3pipectl;
  83         u8 reserved6[60];
  84 };
  85 check_member(usb_dwc3, usb3pipectl, 0x1c0);
  86
  87 struct usb_dwc3_cfg {
  88         struct usb_dwc3 *usb_host_dwc3;
  89         struct usb_usb2_phy_dig *usb2_phy_dig;
  90         struct usb_qscratch *usb_qscratch_reg;
  91         u32 *usb2_phy_bcr;
  92         u32 *usb2_phy_por_bcr;
  93         u32 *usb3_bcr;
  94         struct usb_board_data *board_data;
  95 };
  96
  97 static struct usb_dwc3_cfg usb_host_base[2] = {
  98         [HSUSB_SS_PORT_0] = {
  99         .usb_host_dwc3 =        (void *)USB_HOST0_DWC3_BASE,
 100         .usb2_phy_dig  =        (void *)USB2_FEMTO_PHY_PRI_BASE,
 101         .usb2_phy_bcr =         (void *)GCC_USB_HS_PHY_CFG_AHB_BCR,
 102         .usb2_phy_por_bcr =     (void *)GCC_USB2A_PHY_BCR,
 103         .usb3_bcr =             (void *)GCC_USB_30_BCR,
 104         .usb_qscratch_reg =     (void *)USB3_USB30_QSCRATCH_BASE,
 105         },
 106         [HSUSB_HS_PORT_1] = {
 107         .usb_host_dwc3 =        (void *)USB_HOST1_DWC3_BASE,
 108         .usb2_phy_dig  =        (void *)USB2_FEMTO_PHY_SEC_BASE,
 109         .usb2_phy_bcr =         (void *)GCC_QUSB2_PHY_BCR,
 110         .usb2_phy_por_bcr =     (void *)GCC_USB2_HS_PHY_ONLY_BCR,
 111         .usb3_bcr =             (void *)GCC_USB_HS_BCR,
 112         .usb_qscratch_reg =     (void *)USB2_USB30_QSCRATCH_BASE,
 113         },
 114 };
 115
 116 void reset_usb(enum usb_port port)
 117 {
 118         struct usb_dwc3_cfg *dwc3 = &usb_host_base[port];
 119
 120         /* Put Core in Reset */
 121         printk(BIOS_INFO, "Starting DWC3 reset for USB%d\n", port);
 122
 123         /* Assert Core reset */
 124         clock_reset_bcr(dwc3->usb3_bcr, 1);
 125 }
 126
 127 static void usb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3)
 128 {
 129         /* Override disconnect & squelch threshold values */
 130         write8(&dwc3->usb2_phy_dig->override_x0,
 131                         dwc3->board_data->parameter_override_x0);
 132
 133         /* Override HS transmitter Pre-emphasis values */
 134         write8(&dwc3->usb2_phy_dig->override_x1,
 135                         dwc3->board_data->parameter_override_x1);
 136
 137         /* Override HS transmitter Rise/Fall time values */
 138         write8(&dwc3->usb2_phy_dig->override_x2,
 139                         dwc3->board_data->parameter_override_x2);
 140
 141         /* Override FS/LS Source impedance values */
 142         write8(&dwc3->usb2_phy_dig->override_x3,
 143                         dwc3->board_data->parameter_override_x3);
 144 }
 145
 146 static void hs_usb_phy_init(struct usb_dwc3_cfg *dwc3)
 147 {
 148         write8(&dwc3->usb2_phy_dig->tcsr_ctrl, USB2PHY_TCSR_CTRL);
 149         write8(&dwc3->usb2_phy_dig->refclk_ctrl, USB2PHY_REFCLK_CTRL);
 150         write8(&dwc3->usb2_phy_dig->utmi_ctrl5, USB2PHY_UTMI_CTRL5);
 151         write8(&dwc3->usb2_phy_dig->override_x0, USB2PHY_PARAMETER_OVERRIDE_X0);
 152         write8(&dwc3->usb2_phy_dig->override_x1, USB2PHY_PARAMETER_OVERRIDE_X1);
 153         write8(&dwc3->usb2_phy_dig->override_x2, USB2PHY_PARAMETER_OVERRIDE_X2);
 154         write8(&dwc3->usb2_phy_dig->override_x3, USB2PHY_PARAMETER_OVERRIDE_X3);
 155
 156         if (dwc3->board_data)
 157                 /* Override board specific PHY tuning values */
 158                 usb2_phy_override_phy_params(dwc3);
 159
 160         write8(&dwc3->usb2_phy_dig->phy_ctrl1, USB2PHY_HS_PHY_CTRL1);
 161         write8(&dwc3->usb2_phy_dig->ctrl_common0, QUSB2PHY_HS_PHY_CTRL_COMMON0);
 162         write8(&dwc3->usb2_phy_dig->ctrl_common1, QUSB2PHY_HS_PHY_CTRL_COMMON1);
 163         write8(&dwc3->usb2_phy_dig->phy_ctrl2, USB2PHY_HS_PHY_CTRL2);
 164         udelay(20);
 165         write8(&dwc3->usb2_phy_dig->utmi_ctrl5, USB2PHY_UTMI_CTRL5_POR_CLEAR);
 166         write8(&dwc3->usb2_phy_dig->phy_ctrl2,
 167                                         USB2PHY_HS_PHY_CTRL2_SUSPEND_N_SEL);
 168 }
 169
 170 static void setup_dwc3(struct usb_dwc3 *dwc3)
 171 {
 172         /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */
 173         clrsetbits32(&dwc3->usb3pipectl,
 174                 DWC3_GUSB3PIPECTL_DELAYP1TRANS,
 175                 DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX);
 176
 177         clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK |
 178                         DWC3_GCTL_DISSCRAMBLE),
 179                         DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG);
 180
 181         /* configure controller in Host mode */
 182         clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
 183                         DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST));
 184         printk(BIOS_INFO, "Configure USB in Host mode\n");
 185 }
 186
 187 /* Initialization of DWC3 Core and PHY */
 188 void setup_usb_host(enum usb_port port, struct usb_board_data *board_data)
 189 {
 190         struct usb_dwc3_cfg *dwc3 = &usb_host_base[port];
 191         u32 val;
 192
 193         printk(BIOS_INFO, "Setting up USB HOST%d controller.\n", port);
 194
 195         dwc3->board_data = board_data;
 196
 197          /* Clear core reset. */
 198         clock_reset_bcr(dwc3->usb3_bcr, 0);
 199
 200         if (port == HSUSB_SS_PORT_0) {
 201                 /* Set PHY reset. */
 202                 setbits32(&dwc3->usb2_phy_bcr, BIT(1));
 203                 udelay(15);
 204                 /* Clear PHY reset. */
 205                 clrbits32(&dwc3->usb2_phy_bcr, BIT(1));
 206         } else {
 207                 clock_reset_bcr(dwc3->usb2_phy_bcr, 1);
 208                 udelay(15);
 209                 clock_reset_bcr(dwc3->usb2_phy_bcr, 0);
 210         }
 211         udelay(100);
 212
 213         /* Initialize PHYs */
 214         hs_usb_phy_init(dwc3);
 215
 216         if (port == HSUSB_SS_PORT_0) {
 217                 /* Set PHY POR reset. */
 218                 setbits32(&dwc3->usb2_phy_por_bcr, BIT(0));
 219                 val = read8(&dwc3->usb2_phy_dig->ctrl_common0);
 220                 val &= ~(0x4);
 221                 write8(&dwc3->usb2_phy_dig->ctrl_common0, val);
 222                 udelay(20);
 223                 /* Clear PHY POR reset. */
 224                 clrbits32(&dwc3->usb2_phy_por_bcr, BIT(0));
 225         } else {
 226                 clock_reset_bcr(dwc3->usb2_phy_por_bcr, 1);
 227                 val = read8(&dwc3->usb2_phy_dig->ctrl_common0);
 228                 val &= ~(0x4);
 229                 write8(&dwc3->usb2_phy_dig->ctrl_common0, val);
 230                 udelay(20);
 231                 clock_reset_bcr(dwc3->usb2_phy_por_bcr, 0);
 232         }
 233         udelay(100);
 234
 235         setup_dwc3(dwc3->usb_host_dwc3);
 236
 237         /*
 238          * Below sequence is used when dwc3 operates without
 239          * SSPHY and only HS/FS/LS modes are supported.
 240          */
 241
 242          /* Configure dwc3 to use UTMI clock as PIPE clock not present */
 243         setbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
 244                         PIPE_UTMI_CLK_DIS);
 245         udelay(2);
 246         setbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
 247                         PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
 248         udelay(3);
 249         clrbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
 250                         PIPE_UTMI_CLK_DIS);
 251
 252         printk(BIOS_INFO, "DWC3 and PHY setup finished\n");
 253 }