src/soc/qualcomm/sc7280/clock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <assert.h>
   4 #include <commonlib/helpers.h>
   5 #include <device/mmio.h>
   6 #include <soc/clock.h>
   7 #include <types.h>
   8
   9 static struct clock_freq_config qspi_core_cfg[] = {
  10         {
  11                 .hz = SRC_XO_HZ,        /* 19.2KHz */
  12                 .src = SRC_XO_19_2MHZ,
  13                 .div = QCOM_CLOCK_DIV(1),
  14         },
  15         {
  16                 .hz = 100 * MHz,
  17                 .src = SRC_GPLL0_MAIN_600MHZ,
  18                 .div = QCOM_CLOCK_DIV(6),
  19         },
  20         {
  21                 .hz = 150 * MHz,
  22                 .src = SRC_GPLL0_MAIN_600MHZ,
  23                 .div = QCOM_CLOCK_DIV(4),
  24         },
  25         {
  26                 .hz = 200 * MHz,
  27                 .src = SRC_GPLL0_MAIN_600MHZ,
  28                 .div = QCOM_CLOCK_DIV(3),
  29         },
  30         {
  31                 .hz = 400 * MHz,
  32                 .src = SRC_GPLL0_MAIN_600MHZ,
  33                 .div = QCOM_CLOCK_DIV(1.5),
  34         },
  35 };
  36
  37 static struct clock_freq_config qupv3_wrap_cfg[] = {
  38         {
  39                 .hz = SRC_XO_HZ,        /* 19.2KHz */
  40                 .src = SRC_XO_19_2MHZ,
  41                 .div = QCOM_CLOCK_DIV(1),
  42         },
  43         {
  44                 .hz =  32 * MHz,
  45                 .src = SRC_GPLL0_EVEN_300MHZ,
  46                 .div = QCOM_CLOCK_DIV(1),
  47                 .m = 8,
  48                 .n = 75,
  49                 .d_2 = 75,
  50         },
  51         {
  52                 .hz =  48 * MHz,
  53                 .src = SRC_GPLL0_EVEN_300MHZ,
  54                 .div = QCOM_CLOCK_DIV(1),
  55                 .m = 4,
  56                 .n = 25,
  57                 .d_2 = 25,
  58         },
  59         {
  60                 .hz =  64 * MHz,
  61                 .src = SRC_GPLL0_EVEN_300MHZ,
  62                 .div = QCOM_CLOCK_DIV(1),
  63                 .m = 16,
  64                 .n = 75,
  65                 .d_2 = 75,
  66         },
  67         {
  68                 .hz =  96 * MHz,
  69                 .src = SRC_GPLL0_EVEN_300MHZ,
  70                 .div = QCOM_CLOCK_DIV(1),
  71                 .m = 8,
  72                 .n = 25,
  73                 .d_2 = 25,
  74         },
  75         {
  76                 .hz =  100 * MHz,
  77                 .src = SRC_GPLL0_MAIN_600MHZ,
  78                 .div = QCOM_CLOCK_DIV(6),
  79         },
  80         {
  81                 .hz = SRC_XO_HZ,        /* 19.2KHz */
  82                 .src = SRC_XO_19_2MHZ,
  83                 .div = QCOM_CLOCK_DIV(1),
  84         },
  85         {
  86                 .hz = SRC_XO_HZ,        /* 19.2KHz */
  87                 .src = SRC_XO_19_2MHZ,
  88                 .div = QCOM_CLOCK_DIV(1),
  89         },
  90 };
  91
  92 static struct clock_freq_config sdcc1_core_cfg[] = {
  93         {
  94                 .hz = 100 * MHz,
  95                 .src = SRC_GPLL0_EVEN_300MHZ,
  96                 .div = QCOM_CLOCK_DIV(3),
  97         },
  98         {
  99                 .hz = 192 * MHz,
 100                 .src = SRC_GPLL10_MAIN_384MHZ,
 101                 .div = QCOM_CLOCK_DIV(2),
 102         },
 103         {
 104                 .hz = 384 * MHz,
 105                 .src = SRC_GPLL10_MAIN_384MHZ,
 106                 .div = QCOM_CLOCK_DIV(1),
 107         },
 108 };
 109
 110 static struct clock_freq_config sdcc2_core_cfg[] = {
 111         {
 112                 .hz = 50 * MHz,
 113                 .src = SRC_GPLL0_EVEN_300MHZ,
 114                 .div = QCOM_CLOCK_DIV(6),
 115         },
 116         {
 117                 .hz = 202 * MHz,
 118                 .src = SRC_GPLL9_MAIN_808MHZ,
 119                 .div = QCOM_CLOCK_DIV(4),
 120         },
 121 };
 122
 123 static struct pcie pcie_cfg[] = {
 124         [PCIE_1_GDSC] = {
 125                 .gdscr = &gcc->pcie_1.gdscr,
 126         },
 127         [PCIE_1_SLV_Q2A_AXI_CLK] = {
 128                 .clk = &gcc->pcie_1.slv_q2a_axi_cbcr,
 129                 .clk_br_en = &gcc->apcs_clk_br_en,
 130                 .vote_bit = PCIE_1_SLV_Q2A_AXI_CLK_ENA,
 131         },
 132         [PCIE_1_SLV_AXI_CLK] = {
 133                 .clk = &gcc->pcie_1.slv_axi_cbcr,
 134                 .clk_br_en = &gcc->apcs_clk_br_en,
 135                 .vote_bit = PCIE_1_SLV_AXI_CLK_ENA,
 136         },
 137         [PCIE_1_MSTR_AXI_CLK] = {
 138                 .clk = &gcc->pcie_1.mstr_axi_cbcr,
 139                 .clk_br_en = &gcc->apcs_clk_br_en,
 140                 .vote_bit = PCIE_1_MSTR_AXI_CLK_ENA,
 141         },
 142         [PCIE_1_CFG_AHB_CLK] = {
 143                 .clk = &gcc->pcie_1.cfg_ahb_cbcr,
 144                 .clk_br_en = &gcc->apcs_clk_br_en,
 145                 .vote_bit = PCIE_1_CFG_AHB_CLK_ENA,
 146         },
 147         [PCIE_1_AUX_CLK] = {
 148                 .clk = &gcc->pcie_1.aux_cbcr,
 149                 .clk_br_en = &gcc->apcs_clk_br_en,
 150                 .vote_bit = PCIE_1_AUX_CLK_ENA,
 151         },
 152         [AGGRE_NOC_PCIE_TBU_CLK] = {
 153                 .clk = &gcc->aggre_noc_pcie_tbu_cbcr,
 154                 .clk_br_en = &gcc->apcs_clk_br_en,
 155                 .vote_bit = AGGRE_NOC_PCIE_TBU_CLK_ENA,
 156         },
 157         [AGGRE_NOC_PCIE_1_AXI_CLK] = {
 158                 .clk = &gcc->pcie_1.aggre_noc_pcie_axi_cbcr,
 159                 .clk_br_en = &gcc->apcs_clk_br_en,
 160                 .vote_bit = AGGRE_NOC_PCIE_1_AXI_CLK_ENA,
 161         },
 162         [DDRSS_PCIE_SF_CLK] = {
 163                 .clk = &gcc->pcie_1.ddrss_pcie_sf_cbcr,
 164                 .clk_br_en = &gcc->apcs_clk_br_en,
 165                 .vote_bit = DDRSS_PCIE_SF_CLK_ENA,
 166         },
 167         [PCIE1_PHY_RCHNG_CLK] = {
 168                 .clk = &gcc->pcie_1.phy_rchng_cbcr,
 169                 .clk_br_en = &gcc->apcs_clk_br_en,
 170                 .vote_bit = PCIE1_PHY_RCHNG_CLK_ENA,
 171         },
 172         [AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK] = {
 173                 .clk = &gcc->pcie_1.aggre_noc_pcie_center_sf_axi_cbcr,
 174                 .clk_br_en = &gcc->apcs_clk_br_en1,
 175                 .vote_bit = AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK_ENA,
 176         },
 177         [PCIE_1_PIPE_CLK] = {
 178                 .clk = &gcc->pcie_1.pipe_cbcr,
 179                 .clk_br_en = &gcc->apcs_clk_br_en,
 180                 .vote_bit = PCIE_1_PIPE_CLK_ENA,
 181         },
 182         [PCIE_CLKREF_EN] = {
 183                 .clk = &gcc->pcie_clkref_en,
 184                 .vote_bit = NO_VOTE_BIT,
 185         },
 186         [GCC_PCIE_1_PIPE_MUXR] = {
 187                 .clk = &gcc->pcie_1.pipe_muxr,
 188                 .vote_bit = NO_VOTE_BIT,
 189         },
 190 };
 191
 192 static struct clock_freq_config mdss_mdp_cfg[] = {
 193         {
 194                 .hz = 200 * MHz,
 195                 .src = SRC_GCC_DISP_GPLL0_CLK,
 196                 .div = QCOM_CLOCK_DIV(3),
 197         },
 198         {
 199                 .hz = 300 * MHz,
 200                 .src = SRC_GCC_DISP_GPLL0_CLK,
 201                 .div = QCOM_CLOCK_DIV(2),
 202         },
 203         {
 204                 .hz = 400 * MHz,
 205                 .src = SRC_GCC_DISP_GPLL0_CLK,
 206                 .div = QCOM_CLOCK_DIV(1.5),
 207         },
 208 };
 209
 210 static struct clock_rcg *mdss_clock[MDSS_CLK_COUNT] = {
 211         [MDSS_CLK_MDP] = &mdss->mdp,
 212         [MDSS_CLK_VSYNC] = &mdss->vsync,
 213         [MDSS_CLK_ESC0] = &mdss->esc0,
 214         [MDSS_CLK_BYTE0] = &mdss->byte0,
 215         [MDSS_CLK_BYTE0_INTF] = &mdss->byte0,
 216         [MDSS_CLK_AHB] = &mdss->mdss_ahb,
 217         [MDSS_CLK_EDP_LINK] = &mdss->edp_link,
 218         [MDSS_CLK_EDP_LINK_INTF] = &mdss->edp_link,
 219         [MDSS_CLK_EDP_AUX] = &mdss->edp_aux,
 220 };
 221
 222 static struct clock_rcg_mnd *mdss_clock_mnd[MDSS_CLK_COUNT] = {
 223         [MDSS_CLK_PCLK0] = &mdss->pclk0,
 224         [MDSS_CLK_EDP_PIXEL] = &mdss->edp_pixel,
 225 };
 226
 227 static u32 *mdss_cbcr[MDSS_CLK_COUNT] = {
 228         [GCC_DISP_AHB] = &gcc->disp_ahb_cbcr,
 229         [GCC_DISP_HF_AXI] = &gcc->disp_hf_axi_cbcr,
 230         [GCC_DISP_SF_AXI] = &gcc->disp_sf_axi_cbcr,
 231         [GCC_EDP_CLKREF_EN] = &gcc->edp_clkref_en,
 232         [MDSS_CLK_PCLK0] = &mdss->pclk0_cbcr,
 233         [MDSS_CLK_MDP] = &mdss->mdp_cbcr,
 234         [MDSS_CLK_VSYNC] = &mdss->vsync_cbcr,
 235         [MDSS_CLK_BYTE0] = &mdss->byte0_cbcr,
 236         [MDSS_CLK_BYTE0_INTF] = &mdss->byte0_intf_cbcr,
 237         [MDSS_CLK_ESC0] = &mdss->esc0_cbcr,
 238         [MDSS_CLK_AHB] = &mdss->ahb_cbcr,
 239         [MDSS_CLK_EDP_PIXEL] = &mdss->edp_pixel_cbcr,
 240         [MDSS_CLK_EDP_LINK] = &mdss->edp_link_cbcr,
 241         [MDSS_CLK_EDP_LINK_INTF] = &mdss->edp_link_intf_cbcr,
 242         [MDSS_CLK_EDP_AUX] = &mdss->edp_aux_cbcr,
 243 };
 244
 245 static u32 *gdsc[MAX_GDSC] = {
 246         [PCIE_1_GDSC] = &gcc->pcie_1.gdscr,
 247         [MDSS_CORE_GDSC] = &mdss->core_gdsc,
 248 };
 249
 250 static enum cb_err clock_configure_gpll0(void)
 251 {
 252         struct alpha_pll_reg_val_config gpll0_cfg = {0};
 253
 254         gpll0_cfg.reg_user_ctl = &gcc->gpll0.user_ctl;
 255         gpll0_cfg.user_ctl_val = (1 << PLL_POST_DIV_EVEN_SHFT |
 256                                 3 << PLL_POST_DIV_ODD_SHFT |
 257                                 1 << PLL_PLLOUT_EVEN_SHFT |
 258                                 1 << PLL_PLLOUT_MAIN_SHFT |
 259                                 1 << PLL_PLLOUT_ODD_SHFT);
 260
 261         return clock_configure_enable_gpll(&gpll0_cfg, false, 0);
 262 }
 263
 264 void clock_configure_qspi(uint32_t hz)
 265 {
 266         clock_configure(&gcc->qspi_core,
 267                         qspi_core_cfg, hz,
 268                         ARRAY_SIZE(qspi_core_cfg));
 269         clock_enable(&gcc->qspi_cnoc_ahb_cbcr);
 270         clock_enable(&gcc->qspi_core_cbcr);
 271 }
 272
 273 void clock_enable_qup(int qup)
 274 {
 275         struct qupv3_clock *qup_clk;
 276         int s = qup % QUP_WRAP1_S0, clk_en_off;
 277
 278         qup_clk = qup < QUP_WRAP1_S0 ?
 279                                 &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s];
 280
 281         if (qup < QUP_WRAP1_S6) {
 282                 clk_en_off = qup < QUP_WRAP1_S0 ?
 283                         QUPV3_WRAP0_CLK_ENA_S(s) : QUPV3_WRAP1_CLK_ENA_S(s);
 284                 clock_enable_vote(&qup_clk->cbcr, &gcc->apcs_clk_br_en1,
 285                                                         clk_en_off);
 286         } else {
 287                 clk_en_off = QUPV3_WRAP1_CLK_ENA_1_S(s);
 288                 clock_enable_vote(&qup_clk->cbcr, &gcc->apcs_clk_br_en,
 289                                                                 clk_en_off);
 290         }
 291 }
 292
 293 void clock_configure_sdcc1(uint32_t hz)
 294 {
 295         if (hz > CLK_100MHZ) {
 296                 struct alpha_pll_reg_val_config gpll10_cfg = {0};
 297                 gpll10_cfg.reg_mode = &gcc->gpll10.mode;
 298                 gpll10_cfg.reg_opmode = &gcc->gpll10.opmode;
 299                 gpll10_cfg.reg_l = &gcc->gpll10.l;
 300                 gpll10_cfg.l_val = 0x14;
 301                 gpll10_cfg.reg_cal_l = &gcc->gpll10.cal_l;
 302                 gpll10_cfg.cal_l_val = 0x44;
 303                 gpll10_cfg.fsm_enable = true;
 304                 gpll10_cfg.reg_apcs_pll_br_en = &gcc->apcs_pll_br_en;
 305                 clock_configure_enable_gpll(&gpll10_cfg, true, 9);
 306         }
 307         clock_configure((struct clock_rcg *)&gcc->sdcc1, sdcc1_core_cfg,
 308                         hz, ARRAY_SIZE(sdcc1_core_cfg));
 309         clock_enable(&gcc->sdcc1_ahb_cbcr);
 310         clock_enable(&gcc->sdcc1_apps_cbcr);
 311 }
 312
 313 void clock_configure_sdcc2(uint32_t hz)
 314 {
 315         if (hz > CLK_100MHZ) {
 316                 struct alpha_pll_reg_val_config gpll9_cfg = {0};
 317                 gpll9_cfg.reg_mode = &gcc->gpll9.mode;
 318                 gpll9_cfg.reg_opmode = &gcc->gpll9.opmode;
 319                 gpll9_cfg.reg_alpha = &gcc->gpll9.alpha;
 320                 gpll9_cfg.alpha_val = 0x1555;
 321                 gpll9_cfg.reg_l = &gcc->gpll9.l;
 322                 gpll9_cfg.l_val = 0x2A;
 323                 gpll9_cfg.reg_cal_l = &gcc->gpll9.cal_l;
 324                 gpll9_cfg.cal_l_val = 0x44;
 325                 gpll9_cfg.fsm_enable = true;
 326                 gpll9_cfg.reg_apcs_pll_br_en = &gcc->apcs_pll_br_en;
 327                 clock_configure_enable_gpll(&gpll9_cfg, true, 8);
 328         }
 329         clock_configure((struct clock_rcg *)&gcc->sdcc2, sdcc2_core_cfg,
 330                         hz, ARRAY_SIZE(sdcc2_core_cfg));
 331         clock_enable(&gcc->sdcc2_ahb_cbcr);
 332         clock_enable(&gcc->sdcc2_apps_cbcr);
 333 }
 334
 335 void clock_configure_dfsr(int qup)
 336 {
 337         clock_configure_dfsr_table(qup, qupv3_wrap_cfg,
 338                                         ARRAY_SIZE(qupv3_wrap_cfg));
 339 }
 340
 341 static enum cb_err pll_init_and_set(struct sc7280_apss_clock *apss, u32 l_val)
 342 {
 343         struct alpha_pll_reg_val_config pll_cfg = {0};
 344         int ret;
 345         u32 gfmux_val, regval;
 346
 347         pll_cfg.reg_l = &apss->pll.l;
 348         pll_cfg.l_val = l_val;
 349
 350         pll_cfg.reg_config_ctl = &apss->pll.config_ctl_lo;
 351         pll_cfg.reg_config_ctl_hi = &apss->pll.config_ctl_hi;
 352         pll_cfg.reg_config_ctl_hi1 = &apss->pll.config_ctl_u1;
 353
 354         regval = read32(&apss->pll.config_ctl_lo);
 355         pll_cfg.config_ctl_val =  regval &
 356                                         (~(0x2 << K_P_SHFT | 0x2 << K_I_SHFT));
 357
 358         regval = read32(&apss->pll.config_ctl_hi);
 359         pll_cfg.config_ctl_hi_val =  (regval | (BIT(KLSB_SHFT) |
 360                                 BIT(RON_MODE_SHFT))) & (~(0x4 << KLSB_SHFT));
 361
 362         regval = read32(&apss->pll.config_ctl_u1);
 363         pll_cfg.config_ctl_hi1_val = (regval | BIT(FAST_LOCK_LOW_L_SHFT)) &
 364                                         ~BIT(DCO_BIAS_ADJ_SHFT);
 365
 366         ret = clock_configure_enable_gpll(&pll_cfg, false, 0);
 367         if (ret != CB_SUCCESS)
 368                 return CB_ERR;
 369
 370         pll_cfg.reg_mode = &apss->pll.mode;
 371         pll_cfg.reg_opmode = &apss->pll.opmode;
 372         pll_cfg.reg_user_ctl = &apss->pll.user_ctl;
 373
 374         ret =  zonda_pll_enable(&pll_cfg);
 375         if (ret != CB_SUCCESS)
 376                 return CB_ERR;
 377
 378         gfmux_val = read32(&apss->cfg_gfmux) & ~GFMUX_SRC_SEL_BMSK;
 379         gfmux_val |= APCS_SRC_EARLY;
 380         write32(&apss->cfg_gfmux, gfmux_val);
 381
 382         return CB_SUCCESS;
 383 }
 384
 385 enum cb_err clock_enable_gdsc(enum clk_gdsc gdsc_type)
 386 {
 387         if (gdsc_type > MAX_GDSC)
 388                 return CB_ERR;
 389
 390         return enable_and_poll_gdsc_status(gdsc[gdsc_type]);
 391 }
 392
 393 enum cb_err mdss_clock_configure(enum clk_mdss clk_type, uint32_t hz,
 394                                 uint32_t source, uint32_t divider, uint32_t m,
 395                                 uint32_t n, uint32_t d_2)
 396 {
 397         struct clock_freq_config mdss_clk_cfg;
 398         uint32_t idx;
 399
 400         if (clk_type >= MDSS_CLK_COUNT)
 401                 return CB_ERR;
 402
 403         /* Initialize it with received arguments */
 404         mdss_clk_cfg.div = divider ?  QCOM_CLOCK_DIV(divider) : 0;
 405         mdss_clk_cfg.src = source;
 406         mdss_clk_cfg.m = m;
 407         mdss_clk_cfg.n = n;
 408         mdss_clk_cfg.d_2 = d_2;
 409         mdss_clk_cfg.hz = hz;
 410
 411         if (clk_type == MDSS_CLK_MDP) {
 412                 for (idx = 0; idx < ARRAY_SIZE(mdss_mdp_cfg); idx++) {
 413                         if (hz <= mdss_mdp_cfg[idx].hz) {
 414                                 mdss_clk_cfg.src = mdss_mdp_cfg[idx].src;
 415                                 mdss_clk_cfg.div = mdss_mdp_cfg[idx].div;
 416                                 mdss_clk_cfg.hz = mdss_mdp_cfg[idx].hz;
 417                                 mdss_clk_cfg.m = 0;
 418                                 break;
 419                         }
 420                 }
 421         }
 422
 423         switch (clk_type) {
 424         case MDSS_CLK_EDP_PIXEL:
 425         case MDSS_CLK_PCLK0:
 426                 return clock_configure((struct clock_rcg *)
 427                                        mdss_clock_mnd[clk_type],
 428                                        &mdss_clk_cfg, mdss_clk_cfg.hz, 1);
 429         default:
 430                 return clock_configure(mdss_clock[clk_type],
 431                                        &mdss_clk_cfg, mdss_clk_cfg.hz, 1);
 432         }
 433 }
 434
 435 enum cb_err mdss_clock_enable(enum clk_mdss clk_type)
 436 {
 437         if (clk_type >= MDSS_CLK_COUNT)
 438                 return CB_ERR;
 439
 440         /* Enable clock */
 441         return clock_enable(mdss_cbcr[clk_type]);
 442 }
 443
 444 enum cb_err clock_enable_pcie(enum clk_pcie clk_type)
 445 {
 446         int clk_vote_bit;
 447
 448         if (clk_type >= PCIE_CLK_COUNT)
 449                 return CB_ERR;
 450
 451         clk_vote_bit = pcie_cfg[clk_type].vote_bit;
 452         if (clk_vote_bit < 0)
 453                 return clock_enable(pcie_cfg[clk_type].clk);
 454
 455         clock_enable_vote(pcie_cfg[clk_type].clk,
 456                         pcie_cfg[clk_type].clk_br_en,
 457                         pcie_cfg[clk_type].vote_bit);
 458
 459         return CB_SUCCESS;
 460 }
 461
 462 enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type)
 463 {
 464         if (clk_type >= PCIE_CLK_COUNT)
 465                 return CB_ERR;
 466
 467         /* Set clock src */
 468         write32(pcie_cfg[clk_type].clk, src_type);
 469
 470         return CB_SUCCESS;
 471 }
 472
 473 static void speed_up_boot_cpu(void)
 474 {
 475         /* 1516.8 MHz */
 476         if (!pll_init_and_set(apss_silver, L_VAL_1516P8MHz))
 477                 printk(BIOS_DEBUG, "Silver Frequency bumped to 1.5168(GHz)\n");
 478
 479         /* 1190.4 MHz */
 480         if (!pll_init_and_set(apss_l3, L_VAL_1190P4MHz))
 481                 printk(BIOS_DEBUG, "L3 Frequency bumped to 1.1904(GHz)\n");
 482 }
 483
 484 void clock_init(void)
 485 {
 486         clock_configure_gpll0();
 487
 488         clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr,
 489                                 &gcc->apcs_clk_br_en1,
 490                                 QUPV3_WRAP0_CORE_2X_CLK_ENA);
 491         clock_enable_vote(&gcc->qup_wrap0_core_cbcr,
 492                                 &gcc->apcs_clk_br_en1,
 493                                 QUPV3_WRAP0_CORE_CLK_ENA);
 494         clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr,
 495                                 &gcc->apcs_clk_br_en1,
 496                                 QUPV3_WRAP_0_M_AHB_CLK_ENA);
 497         clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr,
 498                                 &gcc->apcs_clk_br_en1,
 499                                 QUPV3_WRAP_0_S_AHB_CLK_ENA);
 500
 501         clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr,
 502                                 &gcc->apcs_clk_br_en1,
 503                                 QUPV3_WRAP1_CORE_2X_CLK_ENA);
 504         clock_enable_vote(&gcc->qup_wrap1_core_cbcr,
 505                                 &gcc->apcs_clk_br_en1,
 506                                 QUPV3_WRAP1_CORE_CLK_ENA);
 507         clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr,
 508                                 &gcc->apcs_clk_br_en1,
 509                                 QUPV3_WRAP_1_M_AHB_CLK_ENA);
 510         clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr,
 511                                 &gcc->apcs_clk_br_en1,
 512                                 QUPV3_WRAP_1_S_AHB_CLK_ENA);
 513
 514         speed_up_boot_cpu();
 515 }