1 # Protectli Vault FW6 series
3 This page describes how to run coreboot on the [Protectli FW6].
9 The stock firmware contains only the firmware descriptor, BIOS and
10 Management Engine. The EC firmware is not present on the SPI chip.
12 Using ifdtool, a full layout can be obtained along with the ME and FD
15 ## Required proprietary blobs
17 To build a minimal working coreboot image some blobs are required (assuming
18 only the BIOS region is being modified).
21 +-----------------+---------------------------------+---------------------+
22 | Binary file | Apply | Required / Optional |
23 +=================+=================================+=====================+
24 | FSP-M, FSP-S | Intel Firmware Support Package | Required |
25 +-----------------+---------------------------------+---------------------+
26 | microcode | CPU microcode | Required |
27 +-----------------+---------------------------------+---------------------+
28 | vgabios | VGA Option ROM | Optional |
29 +-----------------+---------------------------------+---------------------+
32 FSP-M and FSP-S are obtained after splitting the Kaby Lake FSP binary (done
33 automatically by the coreboot build system and included into the image) from
34 the `3rdparty/fsp` submodule.
36 Microcode updates are automatically included into the coreboot image by build
37 system from the `3rdparty/intel-microcode` submodule.
39 VGA Option ROM is not required to boot, but if one needs graphics in pre-OS
40 stage, it should be included (if not using libgfxinit).
44 ### Internal programming
46 The main SPI flash can be accessed using [flashrom]. The first version
47 supporting the chipset is flashrom v1.1. Firmware an be easily flashed
48 with internal programmer (either BIOS region or full image).
50 The stock firmware can be dumped using [flashrom] or downloaded from
51 Protectli's official [website].
53 ### External programming
55 The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip.
56 This chip is located on the bottom side of the case (the radiator side). One
57 has to remove all screws (in order): 4 top cover screws, 4 side cover screws
58 (one side is enough), 4 mainboard screws, 4 CPU screws (under DIMMs). Lift up
59 the mainboard and turn around it. The flash chip is near the SoC on the DIMM
60 slots side. Use a clip (or solder the wires) to program the chip. Specifically,
61 it's a Macronix MX25L6406E (3.3V) -[datasheet][MX25L6406E].
65 - After flashing with external programmer it is always required to reset RTC
66 with jumper or disconnect coin cell temporarily. Only then the platform will
68 - FW6A does not always work reliably with all DIMMs. Linux happens to hang or
69 gives many panics. This issue was present also with vendor BIOS.
70 - Sometimes FSPMemoryInit return errors or hangs (especially with 2 DIMMs
71 connected). A workaround is to power cycle the board (even a few times) or
72 temporarily disconnect DIMM when platform is powered off.
73 - When using libgfxinit and SeaBIOS bootsplash, the red color is dim.
77 Not all mainboard's peripherals and functions were tested because of lack of
78 the cables or not being populated on the board case.
80 - Internal USB 2.0 headers
84 - USB 3.0 front ports (SeaBIOS and Linux)
86 - HDMI port with libgfxinit and VGA Option ROM
90 - Super I/O serial port 0 (RS232 via front RJ45 connector)
91 - SMBus (reading SPD from DIMMs)
92 - Initialization with KBL FSP 2.0 (with MemoryInit issues)
93 - SeaBIOS payload (version rel-1.12.1)
94 - Mini PCIe debug card connected to mSATA (mSATA slot has LPC signals routed)
96 - Booting Debian, Ubuntu, FreeBSD, Proxmox
97 - PCIe passthrough for NICs and iGPU
98 - Boot with cleaned ME
102 There are 3 variants of FW6 boards: FW6A, FW6B and FW6C. They differ only in
108 +------------------+--------------------------------------------------+
109 | CPU | Intel Celeron 3865U |
110 +------------------+--------------------------------------------------+
111 | PCH | Kaby Lake U w/ iHDCP2.2 Base |
112 +------------------+--------------------------------------------------+
113 | Super I/O, EC | ITE IT8772E |
114 +------------------+--------------------------------------------------+
115 | Coprocessor | Intel Management Engine |
116 +------------------+--------------------------------------------------+
122 +------------------+--------------------------------------------------+
123 | CPU | Intel Core i3-7100U |
124 +------------------+--------------------------------------------------+
125 | PCH | Kaby Lake U w/ iHDCP2.2 Premium |
126 +------------------+--------------------------------------------------+
127 | Super I/O, EC | ITE IT8772E |
128 +------------------+--------------------------------------------------+
129 | Coprocessor | Intel Management Engine |
130 +------------------+--------------------------------------------------+
136 +------------------+--------------------------------------------------+
137 | CPU | Intel Core i5-7200U |
138 +------------------+--------------------------------------------------+
139 | PCH | Kaby Lake U w/ iHDCP2.2 Premium |
140 +------------------+--------------------------------------------------+
141 | Super I/O, EC | ITE IT8772E |
142 +------------------+--------------------------------------------------+
143 | Coprocessor | Intel Management Engine |
144 +------------------+--------------------------------------------------+
147 ## Other compatible boards
149 As Protectli licenses and uses [Yanling] appliances with no modifications
150 to the actual hardware, any compatible [Yanling] appliances would work.
151 Specifically, look for hardware with the same CPU and NIC and coreboot
152 should be able to compile and boot with no modifications required.
154 [Protectli FW6]: https://protectli.com/vault-6-port/
155 [website]: https://protectli.com/kb/coreboot-on-the-vault/
156 [MX25L6406E]: https://www.macronix.com/Lists/Datasheet/Attachments/7370/MX25L6406E,%203V,%2064Mb,%20v1.9.pdf
157 [flashrom]: https://flashrom.org/Flashrom
158 [Yanling]: http://www.ylgkdn.cn/