util/autoport/bd82x6x.go

   1 package main
   2
   3 import (
   4         "fmt"
   5         "os"
   6 )
   7
   8 type bd82x6x struct {
   9         variant string
  10         node    *DevTreeNode
  11 }
  12
  13 func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File,
  14         val uint32, set uint, partno int, constraint uint32) {
  15
  16         max := uint(32)
  17         if set == 3 {
  18                 max = 12
  19         }
  20
  21         bits := [6][2]string{
  22                 {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"},
  23                 {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"},
  24                 {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"},
  25                 {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"},
  26                 {"GPIO_NO_INVERT", "GPIO_INVERT"},
  27                 {"GPIO_NO_BLINK", "GPIO_BLINK"},
  28         }
  29
  30         for i := uint(0); i < max; i++ {
  31                 if (constraint>>i)&1 == 1 {
  32                         fmt.Fprintf(sb, "       .gpio%d = %s,\n",
  33                                 (set-1)*32+i,
  34                                 bits[partno][(val>>i)&1])
  35                 }
  36         }
  37 }
  38
  39 func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) {
  40         var constraint uint32
  41         gpio := Create(ctx, "gpio.c")
  42         defer gpio.Close()
  43
  44         AddBootBlockFile("gpio.c", "")
  45         AddROMStageFile("gpio.c", "")
  46
  47         Add_gpl(gpio)
  48         gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n")
  49
  50         addresses := [3][6]int{
  51                 {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18},
  52                 {0x30, 0x34, 0x38, 0x64, -1, -1},
  53                 {0x40, 0x44, 0x48, 0x68, -1, -1},
  54         }
  55
  56         for set := 1; set <= 3; set++ {
  57                 for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} {
  58                         addr := addresses[set-1][partno]
  59                         if addr < 0 {
  60                                 continue
  61                         }
  62                         fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n",
  63                                 set, set, part)
  64
  65                         constraint = 0xffffffff
  66                         switch part {
  67                         case "direction":
  68                                 /* Ignored on native mode */
  69                                 constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
  70                         case "level":
  71                                 /* Level doesn't matter for input */
  72                                 constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
  73                                 constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
  74                         case "reset":
  75                                 /* Only show reset */
  76                                 constraint = inteltool.GPIO[uint16(addresses[set-1][3])]
  77                         case "invert":
  78                                 /* Only on input and only show inverted GPIO */
  79                                 constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
  80                                 constraint &= inteltool.GPIO[uint16(addresses[set-1][1])]
  81                                 constraint &= inteltool.GPIO[uint16(addresses[set-1][4])]
  82                         case "blink":
  83                                 /* Only on output and only show blinking GPIO */
  84                                 constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
  85                                 constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
  86                                 constraint &= inteltool.GPIO[uint16(addresses[set-1][5])]
  87                         }
  88                         b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint)
  89                         gpio.WriteString("};\n\n")
  90                 }
  91         }
  92
  93         gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = {
  94         .set1 = {
  95                 .mode           = &pch_gpio_set1_mode,
  96                 .direction      = &pch_gpio_set1_direction,
  97                 .level          = &pch_gpio_set1_level,
  98                 .blink          = &pch_gpio_set1_blink,
  99                 .invert         = &pch_gpio_set1_invert,
 100                 .reset          = &pch_gpio_set1_reset,
 101         },
 102         .set2 = {
 103                 .mode           = &pch_gpio_set2_mode,
 104                 .direction      = &pch_gpio_set2_direction,
 105                 .level          = &pch_gpio_set2_level,
 106                 .reset          = &pch_gpio_set2_reset,
 107         },
 108         .set3 = {
 109                 .mode           = &pch_gpio_set3_mode,
 110                 .direction      = &pch_gpio_set3_direction,
 111                 .level          = &pch_gpio_set3_level,
 112                 .reset          = &pch_gpio_set3_reset,
 113         },
 114 };
 115 `)
 116 }
 117
 118 func (b bd82x6x) IsPCIeHotplug(ctx Context, port int) bool {
 119         portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}]
 120         if !ok {
 121                 return false
 122         }
 123         return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0
 124 }
 125
 126 func ich9GetFlashSize(ctx Context) {
 127         inteltool := ctx.InfoSource.GetInteltool()
 128         switch (inteltool.RCBA[0x3410] >> 10) & 3 {
 129         /* SPI. All boards I've seen with sandy/ivy use SPI.  */
 130         case 3:
 131                 ROMProtocol = "SPI"
 132                 highflkb := uint32(0)
 133                 for reg := uint16(0); reg < 5; reg++ {
 134                         fl := (inteltool.RCBA[0x3854+4*reg] >> 16) & 0x1fff
 135                         flkb := (fl + 1) << 2
 136                         if flkb > highflkb {
 137                                 highflkb = flkb
 138                         }
 139                 }
 140                 ROMSizeKB = int(highflkb)
 141                 /* Shared with ME. Flashrom is unable to handle it.  */
 142                 FlashROMSupport = "n"
 143         }
 144 }
 145
 146 func (b bd82x6x) GetGPIOHeader() string {
 147         return "southbridge/intel/bd82x6x/pch.h"
 148 }
 149
 150 func (b bd82x6x) EnableGPE(in int) {
 151         b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2"
 152 }
 153
 154 func (b bd82x6x) EncodeGPE(in int) int {
 155         return in + 0x10
 156 }
 157
 158 func (b bd82x6x) DecodeGPE(in int) int {
 159         return in - 0x10
 160 }
 161
 162 func (b bd82x6x) NeedRouteGPIOManually() {
 163         b.node.Comment += ", FIXME: set gpiX_routing for EC support"
 164 }
 165
 166 func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
 167
 168         SouthBridge = &b
 169
 170         inteltool := ctx.InfoSource.GetInteltool()
 171         b.GPIO(ctx, inteltool)
 172
 173         KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true
 174         KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
 175         KconfigInt["USBDEBUG_HCD_INDEX"] = 2
 176         KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
 177         dmi := ctx.InfoSource.GetDMI()
 178         if dmi.Vendor == "LENOVO" {
 179                 KconfigInt["DRAM_RESET_GATE_GPIO"] = 10
 180         } else {
 181                 KconfigInt["DRAM_RESET_GATE_GPIO"] = 60
 182         }
 183         KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this"
 184
 185         ich9GetFlashSize(ctx)
 186
 187         DSDTDefines = append(DSDTDefines,
 188                 DSDTDefine{
 189                         Key:   "BRIGHTNESS_UP",
 190                         Value: "\\_SB.PCI0.GFX0.INCB",
 191                 },
 192                 DSDTDefine{
 193                         Key:   "BRIGHTNESS_DOWN",
 194                         Value: "\\_SB.PCI0.GFX0.DECB",
 195                 })
 196
 197         /* SPI init */
 198         MainboardIncludes = append(MainboardIncludes, "southbridge/intel/bd82x6x/pch.h")
 199
 200         FADT := ctx.InfoSource.GetACPI()["FACP"]
 201
 202         pcieHotplugMap := "{ "
 203
 204         for port := 0; port < 7; port++ {
 205                 if b.IsPCIeHotplug(ctx, port) {
 206                         pcieHotplugMap += "1, "
 207                 } else {
 208                         pcieHotplugMap += "0, "
 209                 }
 210         }
 211
 212         if b.IsPCIeHotplug(ctx, 7) {
 213                 pcieHotplugMap += "1 }"
 214         } else {
 215                 pcieHotplugMap += "0 }"
 216         }
 217
 218         cur := DevTreeNode{
 219                 Chip:    "southbridge/intel/bd82x6x",
 220                 Comment: "Intel Series 6 Cougar Point PCH",
 221
 222                 Registers: map[string]string{
 223                         "sata_interface_speed_support": "0x3",
 224                         "gen1_dec":                     FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]),
 225                         "gen2_dec":                     FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]),
 226                         "gen3_dec":                     FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]),
 227                         "gen4_dec":                     FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]),
 228                         "pcie_port_coalesce":           "1",
 229                         "pcie_hotplug_map":             pcieHotplugMap,
 230
 231                         "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
 232
 233                         "c2_latency":                 FormatHexLE16(FADT[96:98]),
 234                         "docking_supported":          (FormatBool((FADT[113] & (1 << 1)) != 0)),
 235                         "spi_uvscc":                  fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
 236                         "spi_lvscc":                  fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)),
 237                 },
 238                 PCISlots: []PCISlot{
 239                         PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},
 240                         PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"},
 241                         PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"},
 242                         PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"},
 243                         PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"},
 244                         PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"},
 245                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"},
 246                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"},
 247                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"},
 248                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"},
 249                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"},
 250                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"},
 251                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"},
 252                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"},
 253                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"},
 254                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"},
 255                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"},
 256                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"},
 257                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"},
 258                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"},
 259                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"},
 260                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"},
 261                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"},
 262                 },
 263         }
 264
 265         b.node = &cur
 266
 267         xhciDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}]
 268
 269         if ok {
 270                 cur.Registers["xhci_switchable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xd4:0xd8])
 271                 cur.Registers["superspeed_capable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xdc:0xe0])
 272                 cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4])
 273         }
 274
 275         PutPCIChip(addr, cur)
 276         PutPCIDevParent(addr, "", "lpc")
 277
 278         DSDTIncludes = append(DSDTIncludes, DSDTInclude{
 279                 File: "southbridge/intel/common/acpi/platform.asl",
 280         })
 281         DSDTIncludes = append(DSDTIncludes, DSDTInclude{
 282                 File:  "southbridge/intel/bd82x6x/acpi/globalnvs.asl",
 283         })
 284         DSDTIncludes = append(DSDTIncludes, DSDTInclude{
 285                 File: "southbridge/intel/common/acpi/sleepstates.asl",
 286         })
 287         DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
 288                 File: "southbridge/intel/bd82x6x/acpi/pch.asl",
 289         })
 290
 291         AddBootBlockFile("early_init.c", "")
 292         AddROMStageFile("early_init.c", "")
 293
 294         sb := Create(ctx, "early_init.c")
 295         defer sb.Close()
 296         Add_gpl(sb)
 297
 298         sb.WriteString(`
 299 #include <bootblock_common.h>
 300 #include <northbridge/intel/sandybridge/raminit_native.h>
 301 #include <southbridge/intel/bd82x6x/pch.h>
 302
 303 `)
 304         sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n")
 305
 306         currentMap := map[uint32]int{
 307                 0x20000153: 0,
 308                 0x20000f57: 1,
 309                 0x2000055b: 2,
 310                 0x20000f51: 3,
 311                 0x2000094a: 4,
 312         }
 313
 314         for port := uint(0); port < 14; port++ {
 315                 var pinmask uint32
 316                 OCPin := -1
 317                 if port < 8 {
 318                         pinmask = inteltool.RCBA[0x35a0]
 319                 } else {
 320                         pinmask = inteltool.RCBA[0x35a4]
 321                 }
 322                 for pin := uint(0); pin < 4; pin++ {
 323                         if ((pinmask >> ((port % 8) + 8*pin)) & 1) != 0 {
 324                                 OCPin = int(pin)
 325                                 if port >= 8 {
 326                                         OCPin += 4
 327                                 }
 328                         }
 329                 }
 330                 fmt.Fprintf(sb, "\t{ %d, %d, %d },\n",
 331                         ((inteltool.RCBA[0x359c]>>port)&1)^1,
 332                         currentMap[inteltool.RCBA[uint16(0x3500+4*port)]],
 333                         OCPin)
 334         }
 335         sb.WriteString("};\n")
 336
 337         guessedMap := GuessSPDMap(ctx)
 338
 339         sb.WriteString(`
 340 void bootblock_mainboard_early_init(void)
 341 {
 342 `)
 343         RestorePCI16Simple(sb, addr, 0x82)
 344
 345         RestorePCI16Simple(sb, addr, 0x80)
 346
 347         sb.WriteString(`}
 348
 349 /* FIXME: Put proper SPD map here. */
 350 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 351 {
 352 `)
 353         for i, spd := range guessedMap {
 354                 fmt.Fprintf(sb, "\tread_spd(&spd[%d], 0x%02x, id_only);\n", i, spd)
 355         }
 356         sb.WriteString("}\n")
 357
 358         gnvs := Create(ctx, "acpi_tables.c")
 359         defer gnvs.Close()
 360
 361         Add_gpl(gnvs)
 362         gnvs.WriteString(`#include <southbridge/intel/bd82x6x/nvs.h>
 363
 364 /* FIXME: check this function.  */
 365 void acpi_create_gnvs(struct global_nvs *gnvs)
 366 {
 367         /* The lid is open by default. */
 368         gnvs->lids = 1;
 369
 370         /* Temperature at which OS will shutdown */
 371         gnvs->tcrt = 100;
 372         /* Temperature at which OS will throttle CPU */
 373         gnvs->tpsv = 90;
 374 }
 375 `)
 376 }
 377
 378 func init() {
 379         /* BD82X6X LPC */
 380         for id := 0x1c40; id <= 0x1c5f; id++ {
 381                 RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "BD82X6X"})
 382         }
 383
 384         /* C216 LPC */
 385         for id := 0x1e41; id <= 0x1e5f; id++ {
 386                 RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "C216"})
 387         }
 388
 389         /* PCIe bridge */
 390         for _, id := range []uint16{
 391                 0x1c10, 0x1c12, 0x1c14, 0x1c16,
 392                 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e,
 393                 0x1e10, 0x1e12, 0x1e14, 0x1e16,
 394                 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e,
 395                 0x1e25, 0x244e, 0x2448,
 396         } {
 397                 RegisterPCI(0x8086, id, GenericPCI{})
 398         }
 399
 400         /* SMBus controller  */
 401         RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"})
 402         RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"})
 403
 404         /* SATA */
 405         for _, id := range []uint16{
 406                 0x1c00, 0x1c01, 0x1c02, 0x1c03,
 407                 0x1e00, 0x1e01, 0x1e02, 0x1e03,
 408         } {
 409                 RegisterPCI(0x8086, id, GenericPCI{})
 410         }
 411
 412         /* EHCI */
 413         for _, id := range []uint16{
 414                 0x1c26, 0x1c2d, 0x1e26, 0x1e2d,
 415         } {
 416                 RegisterPCI(0x8086, id, GenericPCI{})
 417         }
 418
 419         /* XHCI */
 420         RegisterPCI(0x8086, 0x1e31, GenericPCI{})
 421
 422         /* ME and children */
 423         for _, id := range []uint16{
 424                 0x1c3a, 0x1c3b, 0x1c3c, 0x1c3d,
 425                 0x1e3a, 0x1e3b, 0x1e3c, 0x1e3d,
 426         } {
 427                 RegisterPCI(0x8086, id, GenericPCI{})
 428         }
 429
 430         /* Ethernet */
 431         RegisterPCI(0x8086, 0x1502, GenericPCI{})
 432         RegisterPCI(0x8086, 0x1503, GenericPCI{})
 433
 434 }