1 /* inteltool - dump all registers on an Intel CPU + chipset based system */
2 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include "inteltool.h"
13 #include "gpio_names/apollolake.h"
14 #include "gpio_names/cannonlake.h"
15 #include "gpio_names/cannonlake_lp.h"
16 #include "gpio_names/denverton.h"
17 #include "gpio_names/icelake.h"
18 #include "gpio_names/lewisburg.h"
19 #include "gpio_names/sunrise.h"
21 #define SBBAR_SIZE (16 * MiB)
22 #define PCR_PORT_SIZE (64 * KiB)
24 static const char *decode_pad_mode(const struct gpio_group
*const group
,
25 const size_t pad
, const uint32_t dw0
)
27 const size_t pad_mode
= dw0
>> 10 & 7;
28 const char *const pad_name
=
29 group
->pad_names
[pad
* group
->func_count
+ pad_mode
];
32 return pad_name
[0] == '*' ? "*GPIO" : "GPIO";
33 else if (pad_mode
< group
->func_count
)
34 return group
->pad_names
[pad
* group
->func_count
+ pad_mode
];
39 static void print_gpio_group(const uint8_t pid
, size_t pad_cfg
,
40 const struct gpio_group
*const group
,
45 printf("%s\n", group
->display
);
47 for (p
= 0; p
< group
->pad_count
; ++p
, pad_cfg
+= pad_stepping
) {
48 const uint32_t dw0
= read_pcr32(pid
, pad_cfg
);
49 const uint32_t dw1
= read_pcr32(pid
, pad_cfg
+ 4);
50 const char *const pad_name
=
51 group
->pad_names
[p
* group
->func_count
];
53 printf("0x%04zx: 0x%016"PRIx64
" %-12s %-20s\n", pad_cfg
,
54 (uint64_t)dw1
<< 32 | dw0
,
55 pad_name
[0] == '*' ? &pad_name
[1] : pad_name
,
56 decode_pad_mode(group
, p
, dw0
));
60 static void print_gpio_community(const struct gpio_community
*const community
,
63 size_t group
, pad_count
;
64 size_t pad_cfg
; /* offset in bytes under this communities PCR port */
66 printf("%s\n\nPCR Port ID: 0x%06zx\n\n",
67 community
->name
, (size_t)community
->pcr_port_id
<< 16);
69 for (group
= 0, pad_count
= 0; group
< community
->group_count
; ++group
)
70 pad_count
+= community
->groups
[group
]->pad_count
;
71 assert(pad_count
* 8 <= PCR_PORT_SIZE
- 0x10);
73 pad_cfg
= read_pcr32(community
->pcr_port_id
, 0x0c);
74 if (pad_cfg
+ pad_count
* 8 > PCR_PORT_SIZE
) {
75 fprintf(stderr
, "Bad Pad Base Address: 0x%08zx\n", pad_cfg
);
79 for (group
= 0; group
< community
->group_count
; ++group
) {
80 print_gpio_group(community
->pcr_port_id
,
81 pad_cfg
, community
->groups
[group
],
83 pad_cfg
+= community
->groups
[group
]->pad_count
* pad_stepping
;
87 const struct gpio_community
*const *get_gpio_communities(struct pci_dev
*const sb
,
88 size_t* community_count
,
93 switch (sb
->device_id
) {
94 case PCI_DEVICE_ID_INTEL_H110
:
95 case PCI_DEVICE_ID_INTEL_H170
:
96 case PCI_DEVICE_ID_INTEL_Z170
:
97 case PCI_DEVICE_ID_INTEL_Q170
:
98 case PCI_DEVICE_ID_INTEL_Q150
:
99 case PCI_DEVICE_ID_INTEL_B150
:
100 case PCI_DEVICE_ID_INTEL_C236
:
101 case PCI_DEVICE_ID_INTEL_C232
:
102 case PCI_DEVICE_ID_INTEL_QM170
:
103 case PCI_DEVICE_ID_INTEL_HM170
:
104 case PCI_DEVICE_ID_INTEL_CM236
:
105 *community_count
= ARRAY_SIZE(sunrise_communities
);
106 return sunrise_communities
;
107 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE
:
108 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL
:
109 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL
:
110 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL
:
111 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL
:
112 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL
:
113 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL
:
114 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE
:
115 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM
:
116 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM
:
117 *community_count
= ARRAY_SIZE(sunrise_lp_communities
);
118 return sunrise_lp_communities
;
119 case PCI_DEVICE_ID_INTEL_C621
:
120 case PCI_DEVICE_ID_INTEL_C622
:
121 case PCI_DEVICE_ID_INTEL_C624
:
122 case PCI_DEVICE_ID_INTEL_C625
:
123 case PCI_DEVICE_ID_INTEL_C626
:
124 case PCI_DEVICE_ID_INTEL_C627
:
125 case PCI_DEVICE_ID_INTEL_C628
:
126 case PCI_DEVICE_ID_INTEL_C629
:
127 case PCI_DEVICE_ID_INTEL_C621A
:
128 case PCI_DEVICE_ID_INTEL_C627A
:
129 case PCI_DEVICE_ID_INTEL_C629A
:
130 case PCI_DEVICE_ID_INTEL_C624_SUPER
:
131 case PCI_DEVICE_ID_INTEL_C627_SUPER_1
:
132 case PCI_DEVICE_ID_INTEL_C621_SUPER
:
133 case PCI_DEVICE_ID_INTEL_C627_SUPER_2
:
134 case PCI_DEVICE_ID_INTEL_C628_SUPER
:
135 case PCI_DEVICE_ID_INTEL_C621A_SUPER
:
136 case PCI_DEVICE_ID_INTEL_C627A_SUPER
:
137 case PCI_DEVICE_ID_INTEL_C629A_SUPER
:
138 *community_count
= ARRAY_SIZE(lewisburg_communities
);
139 return lewisburg_communities
;
140 case PCI_DEVICE_ID_INTEL_DNV_LPC
:
141 *community_count
= ARRAY_SIZE(denverton_communities
);
142 return denverton_communities
;
143 case PCI_DEVICE_ID_INTEL_APL_LPC
:
144 *community_count
= ARRAY_SIZE(apl_communities
);
145 return apl_communities
;
146 case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM
:
147 *community_count
= ARRAY_SIZE(cannonlake_pch_lp_communities
);
149 return cannonlake_pch_lp_communities
;
150 case PCI_DEVICE_ID_INTEL_H310
:
151 case PCI_DEVICE_ID_INTEL_H370
:
152 case PCI_DEVICE_ID_INTEL_Z390
:
153 case PCI_DEVICE_ID_INTEL_Q370
:
154 case PCI_DEVICE_ID_INTEL_B360
:
155 case PCI_DEVICE_ID_INTEL_C246
:
156 case PCI_DEVICE_ID_INTEL_C242
:
157 case PCI_DEVICE_ID_INTEL_QM370
:
158 case PCI_DEVICE_ID_INTEL_HM370
:
159 case PCI_DEVICE_ID_INTEL_CM246
:
160 *community_count
= ARRAY_SIZE(cannonlake_pch_h_communities
);
162 return cannonlake_pch_h_communities
;
163 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U
:
164 *community_count
= ARRAY_SIZE(icelake_pch_h_communities
);
166 return icelake_pch_h_communities
;
172 void print_gpio_groups(struct pci_dev
*const sb
)
174 size_t community_count
;
175 const struct gpio_community
*const *communities
;
178 communities
= get_gpio_communities(sb
, &community_count
, &pad_stepping
);
185 printf("\n============= GPIOS =============\n\n");
187 for (; community_count
; --community_count
)
188 print_gpio_community(*communities
++, pad_stepping
);