util/inteltool/gpio_names/cannonlake.h

   1 #ifndef GPIO_NAMES_CANNONLAKE_H
   2 #define GPIO_NAMES_CANNONLAKE_H
   3
   4 #include "gpio_groups.h"
   5
   6 static const char *const cannonlake_pch_h_group_a_names[] = {
   7         "GPP_A0",       "RCIN#",                "n/a",                  "ESPI_ALERT1#",
   8         "GPP_A1",       "LAD0",                 "n/a",                  "ESPI_IO0",
   9         "GPP_A2",       "LAD1",                 "n/a",                  "ESPI_IO1",
  10         "GPP_A3",       "LAD2",                 "n/a",                  "ESPI_IO2",
  11         "GPP_A4",       "LAD3",                 "n/a",                  "ESPI_IO3",
  12         "GPP_A5",       "LFRAME#",              "n/a",                  "ESPI_CS0#",
  13         "GPP_A6",       "SERIRQ",               "n/a",                  "ESPI_CS1#",
  14         "GPP_A7",       "PIRQA#",               "n/a",                  "ESPI_ALERT0#",
  15         "GPP_A8",       "CLKRUN#",              "n/a",                  "n/a",
  16         "GPP_A9",       "CLKOUT_LPC0",          "n/a",                  "ESPI_CLK",
  17         "GPP_A10",      "CLKOUT_LPC1",          "n/a",                  "n/a",
  18         "GPP_A11",      "PME#",                 "SD_VDD2_PWR_EN#",      "n/a",
  19         "GPP_A12",      "BM_BUSY#",             "ISH_GP6",              "SX_EXIT_HOLDOFF#",
  20         "GPP_A13",      "SUSWARN#/SUSPWRDNACK", "n/a",                  "n/a",
  21         "GPP_A14",      "SUS_STAT#",            "n/a",                  "ESPI_RESET#",
  22         "GPP_A15",      "SUSACK#",              "n/a",                  "n/a",
  23         "GPP_A16",      "CLKOUT_48",            "n/a",                  "n/a",
  24         "GPP_A17",      "SD_VDD1_PWR_EN#",      "ISH_GP7",              "n/a",
  25         "GPP_A18",      "ISH_GP0",              "n/a",                  "n/a",
  26         "GPP_A19",      "ISH_GP1",              "n/a",                  "n/a",
  27         "GPP_A20",      "ISH_GP2",              "n/a",                  "n/a",
  28         "GPP_A21",      "ISH_GP3",              "n/a",                  "n/a",
  29         "GPP_A22",      "ISH_GP4",              "n/a",                  "n/a",
  30         "GPP_A23",      "ISH_GP5",              "n/a",                  "n/a",
  31         "GPIO_RSVD_0",  "n/a",                  "n/a",                  "n/a",
  32 };
  33
  34 static const char *const cannonlake_pch_h_group_b_names[] = {
  35         "GPP_B0",       "GSPI0_CS1#",   "n/a",
  36         "GPP_B1",       "GSPI1_CS1#",   "TIME_SYNC1",
  37         "GPP_B2",       "VRALERT#",     "n/a",
  38         "GPP_B3",       "CPU_GP2",      "n/a",
  39         "GPP_B4",       "CPU_GP3",      "n/a",
  40         "GPP_B5",       "SRCCLKREQ0#",  "n/a",
  41         "GPP_B6",       "SRCCLKREQ1#",  "n/a",
  42         "GPP_B7",       "SRCCLKREQ2#",  "n/a",
  43         "GPP_B8",       "SRCCLKREQ3#",  "n/a",
  44         "GPP_B9",       "SRCCLKREQ4#",  "n/a",
  45         "GPP_B10",      "SRCCLKREQ5#",  "n/a",
  46         "GPP_B11",      "I2S_MCLK",     "n/a",
  47         "GPP_B12",      "SLP_S0#",      "n/a",
  48         "GPP_B13",      "PLTRST#",      "n/a",
  49         "GPP_B14",      "SPKR",         "n/a",
  50         "GPP_B15",      "GSPI0_CS0#",   "n/a",
  51         "GPP_B16",      "GSPI0_CLK",    "n/a",
  52         "GPP_B17",      "GSPI0_MISO",   "n/a",
  53         "GPP_B18",      "GSPI0_MOSI",   "n/a",
  54         "GPP_B19",      "GSPI1_CS0#",   "n/a",
  55         "GPP_B20",      "GSPI1_CLK",    "n/a",
  56         "GPP_B21",      "GSPI1_MISO",   "n/a",
  57         "GPP_B22",      "GSPI1_MOSI",   "n/a",
  58         "GPP_B23",      "SML1ALERT#",   "PCHHOT#",
  59         "GPIO_RSVD_1",  "n/a",          "n/a",
  60         "GPIO_RSVD_2",  "n/a",          "n/a",
  61 };
  62
  63 static const char *const cannonlake_pch_h_group_c_names[] = {
  64         "GPP_C0",       "SMBCLK",       "n/a",
  65         "GPP_C1",       "SMBDATA",      "n/a",
  66         "GPP_C2",       "SMBALERT#",    "n/a",
  67         "GPP_C3",       "SML0CLK",      "n/a",
  68         "GPP_C4",       "SML0DATA",     "n/a",
  69         "GPP_C5",       "SML0ALERT#",   "n/a",
  70         "GPP_C6",       "SML1CLK",      "n/a",
  71         "GPP_C7",       "SML1DATA",     "n/a",
  72         "GPP_C8",       "UART0A_RXD",   "n/a",
  73         "GPP_C9",       "UART0A_TXD",   "n/a",
  74         "GPP_C10",      "UART0A_RTS#",  "n/a",
  75         "GPP_C11",      "UART0A_CTS#",  "n/a",
  76         "GPP_C12",      "UART1_RXD",    "ISH_UART1_RXD",
  77         "GPP_C13",      "UART1_TXD",    "ISH_UART1_TXD",
  78         "GPP_C14",      "UART1_RTS#",   "ISH_UART1_RTS#",
  79         "GPP_C15",      "UART1_CTS#",   "ISH_UART1_CTS#",
  80         "GPP_C16",      "I2C0_SDA",     "n/a",
  81         "GPP_C17",      "I2C0_SCL",     "n/a",
  82         "GPP_C18",      "I2C1_SDA",     "n/a",
  83         "GPP_C19",      "I2C1_SCL",     "n/a",
  84         "GPP_C20",      "UART2_RXD",    "n/a",
  85         "GPP_C21",      "UART2_TXD",    "n/a",
  86         "GPP_C22",      "UART2_RTS#",   "n/a",
  87         "GPP_C23",      "UART2_CTS#",   "n/a",
  88 };
  89
  90 static const char *const cannonlake_pch_h_group_d_names[] = {
  91         "GPP_D0",       "SPI1_CS#",             "n/a",          "SBK0",                 "BK0",
  92         "GPP_D1",       "SPI1_CLK",             "n/a",          "SBK1",                 "BK1",
  93         "GPP_D2",       "SPI1_MISO",            "n/a",          "SBK2",                 "BK2",
  94         "GPP_D3",       "SPI1_MOSI",            "n/a",          "SBK3",                 "BK3",
  95         "GPP_D4",       "I2C2_SDA",             "I2C3_SDA",     "SBK4",                 "BK4",
  96         "GPP_D5",       "I2S2_SFRM",            "n/a",          "CNV_RF_RESET#",        "n/a",
  97         "GPP_D6",       "I2S2_TXD",             "n/a",          "MODEM_CLKREQ",         "n/a",
  98         "GPP_D7",       "I2S2_RXD",             "n/a",          "n/a",                  "n/a",
  99         "GPP_D8",       "I2S2_SCLK",            "n/a",          "n/a",                  "n/a",
 100         "GPP_D9",       "ISH_SPI_CS#",          "n/a",          "GSPI2_CS0#",           "n/a",
 101         "GPP_D10",      "ISH_SPI_CLK",          "n/a",          "GSPI2_CLK",            "n/a",
 102         "GPP_D11",      "ISH_SPI_MISO",         "GP_BSSB_CLK",  "GSPI2_MISO",           "n/a",
 103         "GPP_D12",      "ISH_SPI_MOSI",         "GP_BSSB_DI",   "GSPI2_MOSI",           "n/a",
 104         "GPP_D13",      "ISH_UART0_RXD",        "n/a",          "I2C2_SDA",             "n/a",
 105         "GPP_D14",      "ISH_UART0_TXD",        "n/a",          "I2C2_SCL",             "n/a",
 106         "GPP_D15",      "ISH_UART0_RTS#",       "GSPI2_CS1#",   "n/a",                  "CNV_WFEN",
 107         "GPP_D16",      "ISH_UART0_CTS#",       "n/a",          "n/a",                  "CNV_WCEN",
 108         "GPP_D17",      "DMIC_CLK1",            "SNDW3_CLK",    "n/a",                  "n/a",
 109         "GPP_D18",      "DMIC_DATA1",           "SNDW3_DATA",   "n/a",                  "n/a",
 110         "GPP_D19",      "DMIC_CLK0",            "SNDW4_CLK",    "n/a",                  "n/a",
 111         "GPP_D20",      "DMIC_DATA0",           "SNDW4_DATA",   "n/a",                  "n/a",
 112         "GPP_D21",      "SPI1_IO2",             "n/a",          "n/a",                  "n/a",
 113         "GPP_D22",      "SPI1_IO3",             "n/a",          "n/a",                  "n/a",
 114         "GPP_D23",      "ISH_I2C2_SCL",         "I2C3_SCL",     "n/a",                  "n/a",
 115 };
 116
 117 static const char *const cannonlake_pch_h_group_e_names[] = {
 118         "GPP_E0",       "SATAXPCIE0",   "SATAGP0",
 119         "GPP_E1",       "SATAXPCIE1",   "SATAGP1",
 120         "GPP_E2",       "SATAXPCIE2",   "SATAGP2",
 121         "GPP_E3",       "CPU_GP0",      "n/a",
 122         "GPP_E4",       "SATA_DEVSLP0", "n/a",
 123         "GPP_E5",       "SATA_DEVSLP1", "n/a",
 124         "GPP_E6",       "SATA_DEVSLP2", "n/a",
 125         "GPP_E7",       "CPU_GP1",      "n/a",
 126         "GPP_E8",       "SATALED#",     "n/a",
 127         "GPP_E9",       "USB2_OC0#",    "n/a",
 128         "GPP_E10",      "USB2_OC1#",    "n/a",
 129         "GPP_E11",      "USB2_OC2#",    "n/a",
 130         "GPP_E12",      "USB2_OC3#",    "n/a",
 131 };
 132
 133 static const char *const cannonlake_pch_h_group_f_names[] = {
 134         "GPP_F0",       "SATAXPCIE3",           "SATAGP3",
 135         "GPP_F1",       "SATAXPCIE4",           "SATAGP4",
 136         "GPP_F2",       "SATAXPCIE5",           "SATAGP5",
 137         "GPP_F3",       "SATAXPCIE6",           "SATAGP6",
 138         "GPP_F4",       "SATAXPCIE7",           "SATAGP7",
 139         "GPP_F5",       "SATA_DEVSLP3",         "n/a",
 140         "GPP_F6",       "SATA_DEVSLP4",         "n/a",
 141         "GPP_F7",       "SATA_DEVSLP5",         "n/a",
 142         "GPP_F8",       "SATA_DEVSLP6",         "n/a",
 143         "GPP_F9",       "SATA_DEVSLP7",         "n/a",
 144         "GPP_F10",      "SATA_SCLOCK",          "n/a",
 145         "GPP_F11",      "SATA_SLOAD",           "n/a",
 146         "GPP_F12",      "SATA_SDATAOUT1",       "n/a",
 147         "GPP_F13",      "SATA_SDATAOUT0",       "n/a",
 148         "GPP_F14",      "n/a",                  "PS_ON#",
 149         "GPP_F15",      "USB2_OC4#",            "n/a",
 150         "GPP_F16",      "USB2_OC5#",            "n/a",
 151         "GPP_F17",      "USB2_OC6#",            "n/a",
 152         "GPP_F18",      "USB2_OC7#",            "n/a",
 153         "GPP_F19",      "eDP_VDDEN",            "n/a",
 154         "GPP_F20",      "eDP_BKLTEN",           "n/a",
 155         "GPP_F21",      "eDP_BKLTCTL",          "n/a",
 156         "GPP_F22",      "DDPF_CTRLCLK",         "n/a",
 157         "GPP_F23",      "DDPF_CTRLDATA",        "n/a",
 158 };
 159
 160 static const char *const cannonlake_pch_h_group_spi_names[] = {
 161         "GPIO_RSVD_11",
 162         "GPIO_RSVD_12",
 163         "GPIO_RSVD_13",
 164         "GPIO_RSVD_14",
 165         "GPIO_RSVD_15",
 166         "GPIO_RSVD_16",
 167         "GPIO_RSVD_17",
 168         "GPIO_RSVD_18",
 169         "GPIO_RSVD_19",
 170 };
 171
 172 static const char *const cannonlake_pch_h_group_g_names[] = {
 173         "GPP_G0",       "SD_CMD",
 174         "GPP_G1",       "SD_DATA0",
 175         "GPP_G2",       "SD_DATA1",
 176         "GPP_G3",       "SD_DATA2",
 177         "GPP_G4",       "SD_DATA3",
 178         "GPP_G5",       "SD_CD#",
 179         "GPP_G6",       "SD_CLK",
 180         "GPP_G7",       "SD_WP",
 181 };
 182
 183 static const char *const cannonlake_pch_h_group_aza_names[] = {
 184         "GPIO_RSVD_3",
 185         "GPIO_RSVD_4",
 186         "GPIO_RSVD_5",
 187         "GPIO_RSVD_6",
 188         "GPIO_RSVD_7",
 189         "GPIO_RSVD_8",
 190         "GPIO_RSVD_9",
 191         "GPIO_RSVD_10",
 192 };
 193
 194 static const char *const cannonlake_pch_h_group_vgpio_0_names[] = {
 195         "CNV_BTEN",
 196         "CNV_GNEN",
 197         "CNV_WFEN",
 198         "CNV_WCEN",
 199         "CNV_BT_HOST_WAKEB",
 200         "vCNV_GNSS_HOST_WAKEB",
 201         "vSD3_CD_B",
 202         "CNV_BT_IF_SELECT",
 203         "vCNV_BT_UART_TXD",
 204         "vCNV_BT_UART_RXD",
 205         "vCNV_BT_UART_CTS_B",
 206         "vCNV_BT_UART_RTS_B",
 207         "vCNV_MFUART1_TXD",
 208         "vCNV_MFUART1_RXD",
 209         "vCNV_MFUART1_CTS_B",
 210         "vCNV_MFUART1_RTS_B",
 211         "vCNV_GNSS_UART_TXD",
 212         "vCNV_GNSS_UART_RXD",
 213         "vCNV_GNSS_UART_CTS_B",
 214         "vCNV_GNSS_UART_RTS_B",
 215         "vUART0_TXD",
 216         "vUART0_RXD",
 217         "vUART0_CTS_B",
 218         "vUART0_RTSB",
 219         "vISH_UART0_TXD",
 220         "vISH_UART0_RXD",
 221         "vISH_UART0_CTS_B",
 222         "vISH_UART0_RTSB",
 223         "vISH_UART1_TXD",
 224         "vISH_UART1_RXD",
 225         "vISH_UART1_CTS_B",
 226         "vISH_UART1_RTS_B",
 227 };
 228
 229 static const char *const cannonlake_pch_h_group_vgpio_1_names[] = {
 230         "vCNV_BT_I2S_BCLK",
 231         "vCNV_BT_I2S_WS_SYNC",
 232         "vCNV_BT_I2S_SDO",
 233         "vCNV_BT_I2S_SDI",
 234         "vSSP2_SCLK",
 235         "vSSP2_SFRM",
 236         "vSSP2_TXD",
 237         "vSSP2_RXD",
 238 };
 239
 240 static const char *const cannonlake_pch_h_group_h_names[] = {
 241         "GPP_H0",       "SRCCLKREQ6#",
 242         "GPP_H1",       "SRCCLKREQ7#",
 243         "GPP_H2",       "SRCCLKREQ8#",
 244         "GPP_H3",       "SRCCLKREQ9#",
 245         "GPP_H4",       "SRCCLKREQ10#",
 246         "GPP_H5",       "SRCCLKREQ11#",
 247         "GPP_H6",       "SRCCLKREQ12#",
 248         "GPP_H7",       "SRCCLKREQ13#",
 249         "GPP_H8",       "SRCCLKREQ14#",
 250         "GPP_H9",       "SRCCLKREQ15#",
 251         "GPP_H10",      "SML2CLK",
 252         "GPP_H11",      "SML2DATA",
 253         "GPP_H12",      "SML2ALERT#",
 254         "GPP_H13",      "SML3CLK",
 255         "GPP_H14",      "SML3DATA",
 256         "GPP_H15",      "SML3ALERT#",
 257         "GPP_H16",      "SML4CLK",
 258         "GPP_H17",      "SML4DATA",
 259         "GPP_H18",      "SML4ALERT#",
 260         "GPP_H19",      "ISH_I2C0_SDA",
 261         "GPP_H20",      "ISH_I2C0_SCL",
 262         "GPP_H21",      "ISH_I2C1_SDA",
 263         "GPP_H22",      "ISH_I2C1_SCL",
 264         "GPP_H23",      "TIME_SYNC0",
 265 };
 266
 267 static const char *const cannonlake_pch_h_group_i_names[] = {
 268         "GPP_I0",       "DDPB_HPD0",            "DISP_MISC0",
 269         "GPP_I1",       "DDPB_HPD1",            "DISP_MISC1",
 270         "GPP_I2",       "DDPB_HPD2",            "DISP_MISC2",
 271         "GPP_I3",       "DDPB_HPD3",            "DISP_MISC3",
 272         "GPP_I4",       "EDP_HPD",              "DISP_MISC4",
 273         "GPP_I5",       "DDPB_CTRLCLK",         "n/a",
 274         "GPP_I6",       "DDPB_CTRLDATA",        "n/a",
 275         "GPP_I7",       "DDPC_CTRLCLK",         "n/a",
 276         "GPP_I8",       "DDPC_CTRLDATA",        "n/a",
 277         "GPP_I9",       "DDPD_CTRLCLK",         "n/a",
 278         "GPP_I10",      "DDPD_CTRLDATA",        "n/a",
 279         "GPP_I11",      "M2_SKT2_CFG0",         "n/a",
 280         "GPP_I12",      "M2_SKT2_CFG1",         "n/a",
 281         "GPP_I13",      "M2_SKT2_CFG2",         "n/a",
 282         "GPP_I14",      "M2_SKT2_CFG3",         "n/a",
 283         "GPIO_RSVD_40", "n/a",                  "n/a",
 284         "GPIO_RSVD_41", "n/a",                  "n/a",
 285         "GPIO_RSVD_42", "n/a",                  "n/a",
 286 };
 287
 288 static const char *const cannonlake_pch_h_group_j_names[] = {
 289         "GPP_J0",       "CNV_PA_BLANKING",      "n/a",
 290         "GPP_J1",       "n/a",                  "CPU_C10_GATE#",
 291         "GPP_J2",       "n/a",                  "n/a",
 292         "GPP_J3",       "n/a",                  "n/a",
 293         "GPP_J4",       "CNV_BRI_DT",           "UART0B_RTS#",
 294         "GPP_J5",       "CNV_BRI_RSP",          "UART0B_RXD",
 295         "GPP_J6",       "CNV_RGI_DT",           "UART0B_TXD",
 296         "GPP_J7",       "CNV_RGI_RSP",          "UART0B_CTS#",
 297         "GPP_J8",       "CNV_MFUART2_RXD",      "n/a",
 298         "GPP_J9",       "CNV_MFUART2_TXD",      "n/a",
 299         "GPP_J10",      "n/a",                  "n/a",
 300         "GPP_J11",      "A4WP_PRESENT",         "n/a",
 301 };
 302
 303 static const char *const cannonlake_pch_h_group_k_names[] = {
 304         "GPP_K0",       "n/a",
 305         "GPP_K1",       "n/a",
 306         "GPP_K2",       "n/a",
 307         "GPP_K3",       "n/a",
 308         "GPP_K4",       "n/a",
 309         "GPP_K5",       "n/a",
 310         "GPP_K6",       "n/a",
 311         "GPP_K7",       "n/a",
 312         "GPP_K8",       "Reserved",
 313         "GPP_K9",       "Reserved",
 314         "GPP_K10",      "Reserved",
 315         "GPP_K11",      "Reserved",
 316         "GPP_K12",      "GSXOUT",
 317         "GPP_K13",      "GSXSLOAD",
 318         "GPP_K14",      "GSXDIN",
 319         "GPP_K15",      "GSXSRESET#",
 320         "GPP_K16",      "GSXCLK",
 321         "GPP_K17",      "ADR_COMPLETE",
 322         "GPP_K18",      "NMI#",
 323         "GPP_K19",      "SMI#",
 324         "GPP_K20",      "Reserved",
 325         "GPP_K21",      "Reserved",
 326         "GPP_K22",      "IMGCLKOUT0",
 327         "GPP_K23",      "IMGCLKOUT1",
 328 };
 329
 330 static const char *const cannonlake_pch_h_group_gpd_names[] = {
 331         "GPD0",         "BATLOW#",
 332         "GPD1",         "ACPRESENT",
 333         "GPD2",         "LAN_WAKE#",
 334         "GPD3",         "PRWBTN#",
 335         "GPD4",         "SLP_S3#",
 336         "GPD5",         "SLP_S4#",
 337         "GPD6",         "SLP_A#",
 338         "GPD7",         "n/a",
 339         "GPD8",         "SUSCLK",
 340         "GPD9",         "SLP_WLAN#",
 341         "GPD10",        "SLP_S5#",
 342         "GPD11",        "LANPHYPC",
 343 };
 344
 345 static const struct gpio_group cannonlake_pch_h_group_a = {
 346         .display        = "------- GPIO Group GPP_A -------",
 347         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_a_names) / 4,
 348         .func_count     = 4,
 349         .pad_names      = cannonlake_pch_h_group_a_names,
 350 };
 351
 352 static const struct gpio_group cannonlake_pch_h_group_b = {
 353         .display        = "------- GPIO Group GPP_B -------",
 354         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_b_names) / 3,
 355         .func_count     = 3,
 356         .pad_names      = cannonlake_pch_h_group_b_names,
 357 };
 358
 359 static const struct gpio_group cannonlake_pch_h_group_c = {
 360         .display        = "------- GPIO Group GPP_C -------",
 361         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_c_names) / 3,
 362         .func_count     = 3,
 363         .pad_names      = cannonlake_pch_h_group_c_names,
 364 };
 365
 366 static const struct gpio_group cannonlake_pch_h_group_d = {
 367         .display        = "------- GPIO Group GPP_D -------",
 368         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_d_names) / 5,
 369         .func_count     = 5,
 370         .pad_names      = cannonlake_pch_h_group_d_names,
 371 };
 372
 373 static const struct gpio_group cannonlake_pch_h_group_e = {
 374         .display        = "------- GPIO Group GPP_E -------",
 375         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_e_names) / 3,
 376         .func_count     = 3,
 377         .pad_names      = cannonlake_pch_h_group_e_names,
 378 };
 379
 380 static const struct gpio_group cannonlake_pch_h_group_f = {
 381         .display        = "------- GPIO Group GPP_F -------",
 382         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_f_names) / 3,
 383         .func_count     = 3,
 384         .pad_names      = cannonlake_pch_h_group_f_names,
 385 };
 386
 387 static const struct gpio_group cannonlake_pch_h_group_spi = {
 388         .display        = "------- GPIO Group SPI -------",
 389         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_spi_names) / 1,
 390         .func_count     = 1,
 391         .pad_names      = cannonlake_pch_h_group_spi_names,
 392 };
 393
 394 static const struct gpio_group cannonlake_pch_h_group_g = {
 395         .display        = "------- GPIO Group GPP_G -------",
 396         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_g_names) / 2,
 397         .func_count     = 2,
 398         .pad_names      = cannonlake_pch_h_group_g_names,
 399 };
 400
 401 static const struct gpio_group cannonlake_pch_h_group_aza = {
 402         .display        = "------- GPIO Group AZA -------",
 403         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_aza_names) / 1,
 404         .func_count     = 1,
 405         .pad_names      = cannonlake_pch_h_group_aza_names,
 406 };
 407
 408 static const struct gpio_group cannonlake_pch_h_group_vgpio_0 = {
 409         .display        = "------- GPIO Group VGPIO_0 -------",
 410         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_0_names) / 1,
 411         .func_count     = 1,
 412         .pad_names      = cannonlake_pch_h_group_vgpio_0_names,
 413 };
 414
 415 static const struct gpio_group cannonlake_pch_h_group_vgpio_1 = {
 416         .display        = "------- GPIO Group VGPIO_1 -------",
 417         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_1_names) / 1,
 418         .func_count     = 1,
 419         .pad_names      = cannonlake_pch_h_group_vgpio_1_names,
 420 };
 421
 422 static const struct gpio_group cannonlake_pch_h_group_h = {
 423         .display        = "------- GPIO Group GPP_H -------",
 424         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_h_names) / 2,
 425         .func_count     = 2,
 426         .pad_names      = cannonlake_pch_h_group_h_names,
 427 };
 428
 429 static const struct gpio_group cannonlake_pch_h_group_i = {
 430         .display        = "------- GPIO Group GPP_I -------",
 431         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_i_names) / 3,
 432         .func_count     = 3,
 433         .pad_names      = cannonlake_pch_h_group_i_names,
 434 };
 435
 436 static const struct gpio_group cannonlake_pch_h_group_j = {
 437         .display        = "------- GPIO Group GPP_J -------",
 438         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_j_names) / 3,
 439         .func_count     = 3,
 440         .pad_names      = cannonlake_pch_h_group_j_names,
 441 };
 442
 443 static const struct gpio_group cannonlake_pch_h_group_k = {
 444         .display        = "------- GPIO Group GPP_K -------",
 445         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_k_names) / 2,
 446         .func_count     = 2,
 447         .pad_names      = cannonlake_pch_h_group_k_names,
 448 };
 449
 450 static const struct gpio_group cannonlake_pch_h_group_gpd = {
 451         .display        = "------- GPIO Group GPD -------",
 452         .pad_count      = ARRAY_SIZE(cannonlake_pch_h_group_gpd_names) / 2,
 453         .func_count     = 2,
 454         .pad_names      = cannonlake_pch_h_group_gpd_names,
 455 };
 456
 457 static const struct gpio_group *const cannonlake_pch_h_community_0_groups[] = {
 458         &cannonlake_pch_h_group_a,
 459         &cannonlake_pch_h_group_b,
 460 };
 461 static  const struct gpio_community cannonlake_pch_h_community_0 = {
 462         .name           = "------- GPIO Community 0 -------",
 463         .pcr_port_id    = 0x6e,
 464         .group_count    = ARRAY_SIZE(cannonlake_pch_h_community_0_groups),
 465         .groups         = cannonlake_pch_h_community_0_groups,
 466 };
 467
 468 static const struct gpio_group *const cannonlake_pch_h_community_1_groups[] = {
 469         &cannonlake_pch_h_group_c,
 470         &cannonlake_pch_h_group_d,
 471         &cannonlake_pch_h_group_g,
 472         &cannonlake_pch_h_group_aza,
 473         &cannonlake_pch_h_group_vgpio_0,
 474         &cannonlake_pch_h_group_vgpio_1,
 475 };
 476 static  const struct gpio_community cannonlake_pch_h_community_1 = {
 477         .name           = "------- GPIO Community 1 -------",
 478         .pcr_port_id    = 0x6d,
 479         .group_count    = ARRAY_SIZE(cannonlake_pch_h_community_1_groups),
 480         .groups         = cannonlake_pch_h_community_1_groups,
 481 };
 482
 483 static const struct gpio_group *const cannonlake_pch_h_community_2_groups[] = {
 484         &cannonlake_pch_h_group_gpd,
 485 };
 486 static  const struct gpio_community cannonlake_pch_h_community_2 = {
 487         .name           = "------- GPIO Community 2 -------",
 488         .pcr_port_id    = 0x6c,
 489         .group_count    = ARRAY_SIZE(cannonlake_pch_h_community_2_groups),
 490         .groups         = cannonlake_pch_h_community_2_groups,
 491 };
 492
 493 static const struct gpio_group *const cannonlake_pch_h_community_3_groups[] = {
 494         &cannonlake_pch_h_group_k,
 495         &cannonlake_pch_h_group_h,
 496         &cannonlake_pch_h_group_e,
 497         &cannonlake_pch_h_group_f,
 498         &cannonlake_pch_h_group_spi,
 499 };
 500 static  const struct gpio_community cannonlake_pch_h_community_3 = {
 501         .name           = "------- GPIO Community 3 -------",
 502         .pcr_port_id    = 0x6b,
 503         .group_count    = ARRAY_SIZE(cannonlake_pch_h_community_3_groups),
 504         .groups         = cannonlake_pch_h_community_3_groups,
 505 };
 506
 507 static const struct gpio_group *const cannonlake_pch_h_community_4_groups[] = {
 508         &cannonlake_pch_h_group_i,
 509         &cannonlake_pch_h_group_j,
 510 };
 511 static  const struct gpio_community cannonlake_pch_h_community_4 = {
 512         .name           = "------- GPIO Community 4 -------",
 513         .pcr_port_id    = 0x6a,
 514         .group_count    = ARRAY_SIZE(cannonlake_pch_h_community_4_groups),
 515         .groups         = cannonlake_pch_h_community_4_groups,
 516 };
 517
 518 static const struct gpio_community *const cannonlake_pch_h_communities[] = {
 519         &cannonlake_pch_h_community_0,
 520         &cannonlake_pch_h_community_1,
 521         &cannonlake_pch_h_community_2,
 522         &cannonlake_pch_h_community_3,
 523         &cannonlake_pch_h_community_4,
 524 };
 525
 526 #endif