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mb/ocp/deltalake: Configure FSP DCI via VPD
[coreboot.git] / util / inteltool / pcie.c
blobd392c2810eab02bc4949f31a7a1acdd989724f95
1 /* inteltool - dump all registers on an Intel CPU + chipset based system */
2 /* SPDX-License-Identifier: GPL-2.0-only */
3
4 #include <stdio.h>
5 #include <stdlib.h>
6 #include <inttypes.h>
7 #include "inteltool.h"
8
9 /* 320766 */
10 static const io_register_t nehalem_dmi_registers[] = {
11 { 0x00, 4, "DMIVCH" }, // DMI Virtual Channel Capability Header
12 { 0x04, 4, "DMIVCCAP1" }, // DMI Port VC Capability Register 1
13 { 0x08, 4, "DMIVCCAP2" }, // DMI Port VC Capability Register 2
14 { 0x0C, 4, "DMIVCCTL" }, // DMI Port VC Control
15 { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability
16 { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control
17 /* { 0x18, 2, "RSVD" }, // Reserved */
18 { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status
19 { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability
20 { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control
21 /* { 0x24, 2, "RSVD" }, // Reserved */
22 { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status
23 /* ... - Reserved */
24 { 0x84, 4, "DMILCAP" }, // DMI Link Capabilities
25 { 0x88, 2, "DMILCTL" }, // DMI Link Control
26 { 0x8A, 2, "DMILSTS" }, // DMI Link Status
27 /* ... - Reserved */
28 };
29
30 /* 322812 */
31 static const io_register_t westmere_dmi_registers[] = {
32 { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability
33 { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1
34 { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2
35 { 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control
36 /* { 0x0E, 2, "RSVD" }, // Reserved */
37 { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability
38 { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control
39 /* { 0x18, 2, "RSVD" }, // Reserved */
40 { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status
41 { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability
42 { 0x20, 4, "DMIVC1RCTL1" }, // DMI VC1 Resource Control
43 /* { 0x24, 2, "RSVD" }, // Reserved */
44 { 0x26, 2, "DMIC1RSTS" }, // DMI VC1 Resource Status
45 /* ... - Reserved */
46 { 0x84, 4, "DMILCAP" }, // DMI Link Capabilities
47 { 0x88, 2, "DMILCTL" }, // DMI Link Control
48 { 0x8A, 2, "DMILSTS" }, // DMI Link Status
49 /* ... - Reserved */
50 };
51
52 static const io_register_t sandybridge_dmi_registers[] = {
53 { 0x00, 4, "DMI VCECH" }, // DMI Virtual Channel Enhanced Capability
54 { 0x04, 4, "DMI PVCCAP1" }, // DMI Port VC Capability Register 1
55 { 0x08, 4, "DMI PVVAP2" }, // DMI Port VC Capability Register 2
56 { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control
57 /* { 0x0E, 2, "RSVD" }, // Reserved */
58 { 0x10, 4, "DMI VC0RCAP" }, // DMI VC0 Resource Capability
59 { 0x14, 4, "DMI VC0RCTL" }, // DMI VC0 Resource Control
60 /* { 0x18, 2, "RSVD" }, // Reserved */
61 { 0x1A, 2, "DMI VC0RSTS" }, // DMI VC0 Resource Status
62 { 0x1C, 4, "DMI VC1RCAP" }, // DMI VC1 Resource Capability
63 { 0x20, 4, "DMI VC1RCTL" }, // DMI VC1 Resource Control
64 /* { 0x24, 2, "RSVD" }, // Reserved */
65 { 0x26, 2, "DMI VC1RSTS" }, // DMI VC1 Resource Status
66 { 0x28, 4, "DMI VCPRCAP" }, // DMI VCp Resource Capability
67 { 0x2C, 4, "DMI VCPRCTL" }, // DMI VCp Resource Control
68 /* { 0x30, 2, "RSVD" }, // Reserved */
69 { 0x32, 2, "DMI VCPRSTS" }, // DMI VCp Resource Status
70 { 0x34, 4, "DMI VCMRCAP" }, // DMI VCm Resource Capability
71 { 0x38, 4, "DMI VCMRCTL" }, // DMI VCm Resource Control
72 /* { 0x3C, 2, "RSVD" }, // Reserved */
73 { 0x3E, 2, "DMI VCMRSTS" }, // DMI VCm Resource Status
74 /* { 0x40, 4, "RSVD" }, // Reserved */
75 { 0x44, 4, "DMI ESC" }, // DMI Element Self Description
76 /* { 0x48, 8, "RSVD" }, // Reserved */
77 { 0x50, 4, "DMI LE1D" }, // DMI Link Entry 1 Description
78 /* { 0x54, 4, "RSVD" }, // Reserved */
79 { 0x58, 4, "DMI LE1A" }, // DMI Link Entry 1 Address
80 { 0x5C, 4, "DMI LUE1A" }, // DMI Link Upper Entry 1 Address
81 { 0x60, 4, "DMI LE2D" }, // DMI Link Entry 2 Description
82 /* { 0x64, 4, "RSVD" }, // Reserved */
83 { 0x68, 4, "DMI LE2A" }, // DMI Link Entry 2 Address
84 /* { 0x6C, 4, "RSVD" }, // Reserved
85 { 0x70, 8, "RSVD" }, // Reserved
86 { 0x78, 8, "RSVD" }, // Reserved
87 { 0x80, 4, "RSVD" }, // Reserved */
88 { 0x84, 4, "LCAP" }, // Link Capabilities
89 { 0x88, 2, "LCTL" }, // Link Control
90 { 0x8A, 2, "LSTS" }, // Link Status
91 /* { 0x8C, 4, "RSVD" }, // Reserved
92 { 0x90, 4, "RSVD" }, // Reserved
93 { 0x94, 4, "RSVD" }, // Reserved */
94 { 0x98, 2, "LCTL2" }, // Link Control 2
95 { 0x9A, 2, "LSTS2" }, // Link Status 2
96 /* ... - Reserved */
97 { 0xBC0, 4, "AFE_BMUF0" }, // AFE BMU Configuration Function 0
98 { 0xBC4, 4, "RSVD" }, // Reserved
99 { 0xBC8, 4, "RSVD" }, // Reserved
100 { 0xBCC, 4, "AFE_BMUT0" }, // AFE BMU Configuration Test 0
101 /* ... - Reserved */
102 };
103
104 /*
105 * All Haswell DMI Registers per
106 *
107 * Mobile 4th Generation Intel Core TM Processor Family, Mobile Intel Pentium Processor Family,
108 * and Mobile Intel Celeron Processor Family
109 * Datasheet Volume 2
110 * 329002-002
111 */
112 static const io_register_t haswell_ult_dmi_registers[] = {
113 { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability
114 { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1
115 { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2
116 { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control
117 /* { 0x0E, 2, "RSVD" }, // Reserved */
118 { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability
119 { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control
120 /* { 0x18, 2, "RSVD" }, // Reserved */
121 { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status
122 { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability
123 { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control
124 /* { 0x24, 2, "RSVD" }, // Reserved */
125 { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status
126 { 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability
127 { 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control
128 /* { 0x30, 2, "RSVD" }, // Reserved */
129 { 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status
130 { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability
131 { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control
132 /* { 0x3C, 2, "RSVD" }, // Reserved */
133 { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status
134 { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */
135 { 0x44, 4, "DMIESD" }, // DMI Element Self Description
136 /* { 0x48, 4, "RSVD" }, // Reserved */
137 /* { 0x4C, 4, "RSVD" }, // Reserved */
138 { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description
139 /* { 0x54, 4, "RSVD" }, // Reserved */
140 { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address
141 { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address
142 { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description
143 /* { 0x64, 4, "RSVD" }, // Reserved */
144 { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address
145 /* { 0x6C, 4, "RSVD" }, // Reserved */
146 /* { 0x70, 4, "RSVD" }, // Reserved */
147 /* { 0x74, 4, "RSVD" }, // Reserved */
148 /* { 0x78, 4, "RSVD" }, // Reserved */
149 /* { 0x7C, 4, "RSVD" }, // Reserved */
150 /* { 0x80, 4, "RSVD" }, // Reserved */
151 /* { 0x84, 4, "RSVD" }, // Reserved */
152 { 0x88, 2, "LCTL" }, // Link Control
153 /* ... - Reserved */
154 { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status
155 { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask
156 { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status
157 { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask
158 /* ... - Reserved */
159 };
160
161 /*
162 * All Skylake-S/H DMI Registers per
163 *
164 * 6th Generation Intel Processor Families for S-Platform Volume 2 of 2
165 * Page 117
166 * 332688-003E
167 *
168 * 6th Generation Intel Processor Families for H-Platform Volume 2 of 2
169 * Page 117
170 * 332987-002EN
171 */
172 static const io_register_t skylake_dmi_registers[] = {
173 { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability
174 { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1
175 { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2
176 { 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control
177 { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability
178 { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control
179 { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status
180 { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability
181 { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control
182 { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status
183 { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability
184 { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control
185 { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status
186 { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */
187 { 0x44, 4, "DMIESD" }, // DMI Element Self Description
188 { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description
189 { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address
190 { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address
191 { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description
192 { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address
193 { 0x84, 4, "LCAP" }, // Link Capabilities
194 { 0x88, 2, "LCTL" }, // Link Control
195 { 0x8A, 2, "LSTS" }, // DMI Link Status
196 { 0x98, 2, "LCTL2" }, // Link Control 2
197 { 0x9A, 2, "LSTS2" }, // DMI Link Status 2
198 { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status
199 { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask
200 { 0x1CC, 4, "DMIUESEV" }, // DMI Uncorrectable Error Mask
201 { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status
202 { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask
203 };
204
205
206 /*
207 * Egress Port Root Complex MMIO configuration space
208 */
209 int print_epbar(struct pci_dev *nb)
210 {
211 int i, size = (4 * 1024);
212 volatile uint8_t *epbar;
213 uint64_t epbar_phys;
214
215 printf("\n============= EPBAR =============\n\n");
216
217 switch (nb->device_id) {
218 case PCI_DEVICE_ID_INTEL_82915:
219 case PCI_DEVICE_ID_INTEL_82945GM:
220 case PCI_DEVICE_ID_INTEL_82945GSE:
221 case PCI_DEVICE_ID_INTEL_82945P:
222 case PCI_DEVICE_ID_INTEL_82946:
223 case PCI_DEVICE_ID_INTEL_82975X:
224 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
225 break;
226 case PCI_DEVICE_ID_INTEL_82965PM:
227 case PCI_DEVICE_ID_INTEL_82Q965:
228 case PCI_DEVICE_ID_INTEL_82Q35:
229 case PCI_DEVICE_ID_INTEL_82G33:
230 case PCI_DEVICE_ID_INTEL_82Q33:
231 case PCI_DEVICE_ID_INTEL_82X38:
232 case PCI_DEVICE_ID_INTEL_32X0:
233 case PCI_DEVICE_ID_INTEL_82XX4X:
234 case PCI_DEVICE_ID_INTEL_82Q45:
235 case PCI_DEVICE_ID_INTEL_82G45:
236 case PCI_DEVICE_ID_INTEL_82G41:
237 case PCI_DEVICE_ID_INTEL_82B43:
238 case PCI_DEVICE_ID_INTEL_82B43_2:
239 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
240 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
241 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
242 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
243 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
244 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
245 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
246 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
247 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
248 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D:
249 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
250 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
251 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
252 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
253 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2:
254 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U:
255 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y:
256 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
257 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
258 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
259 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E:
260 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U:
261 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y:
262 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
263 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3:
264 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1:
265 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2:
266 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
267 epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
268 break;
269 case PCI_DEVICE_ID_INTEL_82810:
270 case PCI_DEVICE_ID_INTEL_82810_DC:
271 case PCI_DEVICE_ID_INTEL_82810E_DC:
272 case PCI_DEVICE_ID_INTEL_82830M:
273 case PCI_DEVICE_ID_INTEL_82865:
274 printf("This northbridge does not have EPBAR.\n");
275 return 1;
276 default:
277 printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
278 return 1;
279 }
280
281 epbar = map_physical(epbar_phys, size);
282
283 if (epbar == NULL) {
284 perror("Error mapping EPBAR");
285 exit(1);
286 }
287
288 printf("EPBAR = 0x%08" PRIx64 " (MEM)\n\n", epbar_phys);
289 for (i = 0; i < size; i += 4) {
290 if (read32(epbar + i))
291 printf("0x%04x: 0x%08x\n", i, read32(epbar+i));
292 }
293
294 unmap_physical((void *)epbar, size);
295 return 0;
296 }
297
298 /*
299 * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
300 */
301 int print_dmibar(struct pci_dev *nb)
302 {
303 int i, size = (4 * 1024);
304 volatile uint8_t *dmibar;
305 uint64_t dmibar_phys;
306 const io_register_t *dmi_registers = NULL;
307
308 printf("\n============= DMIBAR ============\n\n");
309
310 switch (nb->device_id) {
311 case PCI_DEVICE_ID_INTEL_82915:
312 case PCI_DEVICE_ID_INTEL_82945GM:
313 case PCI_DEVICE_ID_INTEL_82945GSE:
314 case PCI_DEVICE_ID_INTEL_82945P:
315 case PCI_DEVICE_ID_INTEL_82975X:
316 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
317 break;
318 case PCI_DEVICE_ID_INTEL_82946:
319 case PCI_DEVICE_ID_INTEL_82965PM:
320 case PCI_DEVICE_ID_INTEL_82Q965:
321 case PCI_DEVICE_ID_INTEL_82Q35:
322 case PCI_DEVICE_ID_INTEL_82G33:
323 case PCI_DEVICE_ID_INTEL_82Q33:
324 case PCI_DEVICE_ID_INTEL_82X38:
325 case PCI_DEVICE_ID_INTEL_32X0:
326 case PCI_DEVICE_ID_INTEL_82XX4X:
327 case PCI_DEVICE_ID_INTEL_82Q45:
328 case PCI_DEVICE_ID_INTEL_82G45:
329 case PCI_DEVICE_ID_INTEL_82G41:
330 case PCI_DEVICE_ID_INTEL_82B43:
331 case PCI_DEVICE_ID_INTEL_82B43_2:
332 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
333 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
334 dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
335 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
336 break;
337 case PCI_DEVICE_ID_INTEL_82810:
338 case PCI_DEVICE_ID_INTEL_82810_DC:
339 case PCI_DEVICE_ID_INTEL_82810E_DC:
340 case PCI_DEVICE_ID_INTEL_82865:
341 printf("This northbridge does not have DMIBAR.\n");
342 return 1;
343 case PCI_DEVICE_ID_INTEL_82X58:
344 dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
345 break;
346 case PCI_DEVICE_ID_INTEL_CORE_0TH_GEN:
347 /* DMIBAR is called DMIRCBAR in Nehalem */
348 dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; /* 31:12 */
349 dmi_registers = nehalem_dmi_registers;
350 size = ARRAY_SIZE(nehalem_dmi_registers);
351 break;
352 case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
353 dmibar_phys = pci_read_long(nb, 0x68);
354 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
355 dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */
356 dmi_registers = westmere_dmi_registers;
357 size = ARRAY_SIZE(westmere_dmi_registers);
358 break;
359 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
360 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
361 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
362 dmi_registers = sandybridge_dmi_registers;
363 size = ARRAY_SIZE(sandybridge_dmi_registers);
364 /* fall through */
365 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: /* pretty printing not implemented yet */
366 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
367 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
368 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
369 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D:
370 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
371 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
372 dmibar_phys = pci_read_long(nb, 0x68);
373 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
374 dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
375 break;
376 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
377 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
378 dmi_registers = haswell_ult_dmi_registers;
379 size = ARRAY_SIZE(haswell_ult_dmi_registers);
380 dmibar_phys = pci_read_long(nb, 0x68);
381 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
382 dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
383 break;
384 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2:
385 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U:
386 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y:
387 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
388 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
389 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
390 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E:
391 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U:
392 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y:
393 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
394 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3:
395 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1:
396 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2:
397 dmi_registers = skylake_dmi_registers;
398 size = ARRAY_SIZE(skylake_dmi_registers);
399 dmibar_phys = pci_read_long(nb, 0x68);
400 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
401 dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
402 break;
403 default:
404 printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
405 return 1;
406 }
407
408 dmibar = map_physical(dmibar_phys, size);
409
410 if (dmibar == NULL) {
411 perror("Error mapping DMIBAR");
412 exit(1);
413 }
414
415 printf("DMIBAR = 0x%08" PRIx64 " (MEM)\n\n", dmibar_phys);
416 if (dmi_registers != NULL) {
417 for (i = 0; i < size; i++) {
418 switch (dmi_registers[i].size) {
419 case 4:
420 printf("dmibase+0x%04x: 0x%08x (%s)\n",
421 dmi_registers[i].addr,
422 read32(dmibar+dmi_registers[i].addr),
423 dmi_registers[i].name);
424 break;
425 case 2:
426 printf("dmibase+0x%04x: 0x%04x (%s)\n",
427 dmi_registers[i].addr,
428 read16(dmibar+dmi_registers[i].addr),
429 dmi_registers[i].name);
430 break;
431 case 1:
432 printf("dmibase+0x%04x: 0x%02x (%s)\n",
433 dmi_registers[i].addr,
434 read8(dmibar+dmi_registers[i].addr),
435 dmi_registers[i].name);
436 break;
437 }
438 }
439 } else {
440 for (i = 0; i < size; i += 4) {
441 if (read32(dmibar + i))
442 printf("0x%04x: 0x%08x\n", i, read32(dmibar+i));
443 }
444 }
445
446 unmap_physical((void *)dmibar, size);
447 return 0;
448 }
449
450 /*
451 * PCIe MMIO configuration space
452 */
453 int print_pciexbar(struct pci_dev *nb)
454 {
455 uint64_t pciexbar_reg;
456 uint64_t pciexbar_phys;
457 volatile uint8_t *pciexbar;
458 int max_busses, devbase, i;
459 int bus, dev, fn;
460
461 printf("========= PCIEXBAR ========\n\n");
462
463 switch (nb->device_id) {
464 case PCI_DEVICE_ID_INTEL_82915:
465 case PCI_DEVICE_ID_INTEL_82945GM:
466 case PCI_DEVICE_ID_INTEL_82945GSE:
467 case PCI_DEVICE_ID_INTEL_82945P:
468 case PCI_DEVICE_ID_INTEL_82975X:
469 pciexbar_reg = pci_read_long(nb, 0x48);
470 break;
471 case PCI_DEVICE_ID_INTEL_82946:
472 case PCI_DEVICE_ID_INTEL_82965PM:
473 case PCI_DEVICE_ID_INTEL_82Q965:
474 case PCI_DEVICE_ID_INTEL_82Q35:
475 case PCI_DEVICE_ID_INTEL_82G33:
476 case PCI_DEVICE_ID_INTEL_82Q33:
477 case PCI_DEVICE_ID_INTEL_82X38:
478 case PCI_DEVICE_ID_INTEL_32X0:
479 case PCI_DEVICE_ID_INTEL_82XX4X:
480 case PCI_DEVICE_ID_INTEL_82Q45:
481 case PCI_DEVICE_ID_INTEL_82G45:
482 case PCI_DEVICE_ID_INTEL_82G41:
483 case PCI_DEVICE_ID_INTEL_82B43:
484 case PCI_DEVICE_ID_INTEL_82B43_2:
485 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
486 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
487 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
488 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
489 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
490 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
491 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
492 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
493 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
494 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D:
495 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
496 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
497 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
498 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
499 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2:
500 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U:
501 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y:
502 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
503 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
504 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
505 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E:
506 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U:
507 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y:
508 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
509 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3:
510 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1:
511 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2:
512 pciexbar_reg = pci_read_long(nb, 0x60);
513 pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
514 break;
515 case PCI_DEVICE_ID_INTEL_82810:
516 case PCI_DEVICE_ID_INTEL_82810_DC:
517 case PCI_DEVICE_ID_INTEL_82810E_DC:
518 case PCI_DEVICE_ID_INTEL_82865:
519 printf("Error: This northbridge does not have PCIEXBAR.\n");
520 return 1;
521 default:
522 printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
523 return 1;
524 }
525
526 if (!(pciexbar_reg & (1 << 0))) {
527 printf("PCIEXBAR register is disabled.\n");
528 return 0;
529 }
530
531 switch ((pciexbar_reg >> 1) & 3) {
532 case 0: // 256MB
533 pciexbar_phys = pciexbar_reg & (0xffULL << 28);
534 max_busses = 256;
535 break;
536 case 1: // 128M
537 pciexbar_phys = pciexbar_reg & (0x1ffULL << 27);
538 max_busses = 128;
539 break;
540 case 2: // 64M
541 pciexbar_phys = pciexbar_reg & (0x3ffULL << 26);
542 max_busses = 64;
543 break;
544 default: // RSVD
545 printf("Undefined address base. Bailing out.\n");
546 return 1;
547 }
548
549 printf("PCIEXBAR: 0x%08" PRIx64 "\n", pciexbar_phys);
550
551 pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024));
552
553 if (pciexbar == NULL) {
554 perror("Error mapping PCIEXBAR");
555 exit(1);
556 }
557
558 for (bus = 0; bus < max_busses; bus++) {
559 for (dev = 0; dev < 32; dev++) {
560 for (fn = 0; fn < 8; fn++) {
561 devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
562
563 if (read16(pciexbar + devbase) == 0xffff)
564 continue;
565
566 /* This is a heuristics. Anyone got a better check? */
567 if( (read32(pciexbar + devbase + 256) == 0xffffffff) &&
568 (read32(pciexbar + devbase + 512) == 0xffffffff) ) {
569 #if DEBUG
570 printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
571 #endif
572 continue;
573 }
574
575 printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
576 for (i = 0; i < 4096; i++) {
577 if((i % 0x10) == 0)
578 printf("\n%04x:", i);
579 printf(" %02x", *(pciexbar+devbase+i));
580 }
581 printf("\n");
582 }
583 }
584 }
585
586 unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024));
587
588 return 0;
589 }
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