util/inteltool/pcr.c

   1 /* inteltool - dump all registers on an Intel CPU + chipset based system */
   2 /* SPDX-License-Identifier: GPL-2.0-only */
   3
   4 #include <stdio.h>
   5 #include <stdlib.h>
   6 #include <stdint.h>
   7 #include <stdbool.h>
   8 #include <inttypes.h>
   9 #include <assert.h>
  10 #include "pcr.h"
  11
  12 const uint8_t *sbbar = NULL;
  13
  14 uint32_t read_pcr32(const uint8_t port, const uint16_t offset)
  15 {
  16         assert(sbbar);
  17         return *(const uint32_t *)(sbbar + (port << 16) + offset);
  18 }
  19
  20 static void print_pcr_port(const uint8_t port)
  21 {
  22         size_t i = 0;
  23         uint32_t last_reg = 0;
  24         bool last_printed = true;
  25
  26         printf("PCR port offset: 0x%06zx\n\n", (size_t)port << 16);
  27
  28         for (i = 0; i < PCR_PORT_SIZE; i += 4) {
  29                 const uint32_t reg = read_pcr32(port, i);
  30                 const bool rep = i && last_reg == reg;
  31                 if (!rep) {
  32                         if (!last_printed)
  33                                 printf("*\n");
  34                         printf("0x%04zx: 0x%08"PRIx32"\n", i, reg);
  35                 }
  36
  37                 last_reg = reg;
  38                 last_printed = !rep;
  39         }
  40         if (!last_printed)
  41                 printf("*\n");
  42 }
  43
  44 void print_pcr_ports(struct pci_dev *const sb,
  45                      const uint8_t *const ports, const size_t count)
  46 {
  47         size_t i;
  48
  49         pcr_init(sb);
  50
  51         for (i = 0; i < count; ++i) {
  52                 printf("\n========== PCR 0x%02x ==========\n\n", ports[i]);
  53                 print_pcr_port(ports[i]);
  54         }
  55 }
  56
  57 void pcr_init(struct pci_dev *const sb)
  58 {
  59         bool error_exit = false;
  60         bool p2sb_revealed = false;
  61         struct pci_dev *p2sb;
  62         bool use_p2sb = true;
  63         pciaddr_t sbbar_phys;
  64
  65         if (sbbar)
  66                 return;
  67
  68         switch (sb->device_id) {
  69         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE:
  70         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
  71         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
  72         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
  73         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
  74         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
  75         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
  76         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
  77         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
  78         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
  79         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
  80         case PCI_DEVICE_ID_INTEL_H110:
  81         case PCI_DEVICE_ID_INTEL_H170:
  82         case PCI_DEVICE_ID_INTEL_Z170:
  83         case PCI_DEVICE_ID_INTEL_Q170:
  84         case PCI_DEVICE_ID_INTEL_Q150:
  85         case PCI_DEVICE_ID_INTEL_B150:
  86         case PCI_DEVICE_ID_INTEL_C236:
  87         case PCI_DEVICE_ID_INTEL_C232:
  88         case PCI_DEVICE_ID_INTEL_QM170:
  89         case PCI_DEVICE_ID_INTEL_HM170:
  90         case PCI_DEVICE_ID_INTEL_CM236:
  91         case PCI_DEVICE_ID_INTEL_HM175:
  92         case PCI_DEVICE_ID_INTEL_QM175:
  93         case PCI_DEVICE_ID_INTEL_CM238:
  94         case PCI_DEVICE_ID_INTEL_C621:
  95         case PCI_DEVICE_ID_INTEL_C622:
  96         case PCI_DEVICE_ID_INTEL_C624:
  97         case PCI_DEVICE_ID_INTEL_C625:
  98         case PCI_DEVICE_ID_INTEL_C626:
  99         case PCI_DEVICE_ID_INTEL_C627:
 100         case PCI_DEVICE_ID_INTEL_C628:
 101         case PCI_DEVICE_ID_INTEL_C629:
 102         case PCI_DEVICE_ID_INTEL_C624_SUPER:
 103         case PCI_DEVICE_ID_INTEL_C627_SUPER_1:
 104         case PCI_DEVICE_ID_INTEL_C621_SUPER:
 105         case PCI_DEVICE_ID_INTEL_C627_SUPER_2:
 106         case PCI_DEVICE_ID_INTEL_C628_SUPER:
 107         case PCI_DEVICE_ID_INTEL_DNV_LPC:
 108                 p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1);
 109                 break;
 110         case PCI_DEVICE_ID_INTEL_APL_LPC:
 111                 p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0);
 112                 break;
 113         case PCI_DEVICE_ID_INTEL_H310:
 114         case PCI_DEVICE_ID_INTEL_H370:
 115         case PCI_DEVICE_ID_INTEL_Z390:
 116         case PCI_DEVICE_ID_INTEL_Q370:
 117         case PCI_DEVICE_ID_INTEL_B360:
 118         case PCI_DEVICE_ID_INTEL_C246:
 119         case PCI_DEVICE_ID_INTEL_C242:
 120         case PCI_DEVICE_ID_INTEL_QM370:
 121         case PCI_DEVICE_ID_INTEL_HM370:
 122         case PCI_DEVICE_ID_INTEL_CM246:
 123         case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
 124         case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U:
 125                 sbbar_phys = 0xfd000000;
 126                 use_p2sb = false;
 127                 break;
 128         default:
 129                 perror("Unknown LPC device.");
 130                 exit(1);
 131         }
 132
 133         if (use_p2sb) {
 134                 if (!p2sb) {
 135                         perror("Can't allocate device node for P2SB.");
 136                         exit(1);
 137                 }
 138
 139                 /* do not fill bases here, libpci refuses to refill later */
 140                 pci_fill_info(p2sb, PCI_FILL_IDENT);
 141                 if (p2sb->vendor_id == 0xffff && p2sb->device_id == 0xffff) {
 142                         printf("Trying to reveal Primary to Sideband Bridge "
 143                                "(P2SB),\nlet's hope the OS doesn't mind... ");
 144                         /* Do not use pci_write_long(). Bytes
 145                            surrounding 0xe0 must be maintained. */
 146                         pci_write_byte(p2sb, 0xe0 + 1, 0);
 147
 148                         pci_fill_info(p2sb, PCI_FILL_IDENT | PCI_FILL_RESCAN);
 149                         if (p2sb->vendor_id != 0xffff ||
 150                             p2sb->device_id != 0xffff) {
 151                                 printf("done.\n");
 152                                 p2sb_revealed = true;
 153                         } else {
 154                                 printf("failed.\n");
 155                                 exit(1);
 156                         }
 157                 }
 158                 pci_fill_info(p2sb, PCI_FILL_BASES | PCI_FILL_CLASS);
 159
 160                 sbbar_phys = p2sb->base_addr[0] & ~0xfULL;
 161         }
 162
 163         printf("SBREG_BAR = 0x%08"PRIx64" (MEM)\n\n", (uint64_t)sbbar_phys);
 164         sbbar = map_physical(sbbar_phys, SBBAR_SIZE);
 165         if (sbbar == NULL) {
 166                 perror("Error mapping SBREG_BAR");
 167                 error_exit = true;
 168         }
 169
 170         if (use_p2sb) {
 171                 if (p2sb_revealed) {
 172                         printf("Hiding Primary to Sideband Bridge (P2SB).\n");
 173                         pci_write_byte(p2sb, 0xe0 + 1, 1);
 174                 }
 175                 pci_free_dev(p2sb);
 176         }
 177
 178         if (error_exit)
 179                 exit(1);
 180 }
 181
 182 void pcr_cleanup(void)
 183 {
 184         if (sbbar)
 185                 unmap_physical((void *)sbbar, SBBAR_SIZE);
 186 }