?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mb/ocp/deltalake: Configure FSP DCI via VPD
[coreboot.git] / util / mainboard / google / puff / template / overridetree.cb
blob244e67840b0c16d608ff98244fb415d0e8ee7245
1 chip soc/intel/cannonlake
2 # Enable heci communication
3 register "HeciEnabled" = "1"
4
5 # Auto-switch between X4 NVMe and X2 NVMe.
6 register "TetonGlacierMode" = "1"
7
8 register "SerialIoDevMode" = "{
9 [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
10 [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
11 [PchSerialIoIndexI2C2] = PchSerialIoPci,
12 [PchSerialIoIndexI2C3] = PchSerialIoPci,
13 [PchSerialIoIndexI2C4] = PchSerialIoPci,
14 [PchSerialIoIndexI2C5] = PchSerialIoPci,
15 [PchSerialIoIndexSPI0] = PchSerialIoPci,
16 [PchSerialIoIndexSPI1] = PchSerialIoPci,
17 [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
18 [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
19 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
20 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
21 }"
22
23 # USB configuration
24 register "usb2_ports[0]" = "{
25 .enable = 1,
26 .ocpin = OC2,
27 .tx_bias = USB2_BIAS_0MV,
28 .tx_emp_enable = USB2_PRE_EMP_ON,
29 .pre_emp_bias = USB2_BIAS_11P25MV,
30 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
31 }" # Type-A Port 2
32 register "usb2_ports[1]" = "{
33 .enable = 1,
34 .ocpin = OC1,
35 .tx_bias = USB2_BIAS_0MV,
36 .tx_emp_enable = USB2_PRE_EMP_ON,
37 .pre_emp_bias = USB2_BIAS_28P15MV,
38 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
39 }" # Type-A Port 1
40 register "usb2_ports[2]" = "{
41 .enable = 1,
42 .ocpin = OC3,
43 .tx_bias = USB2_BIAS_0MV,
44 .tx_emp_enable = USB2_PRE_EMP_ON,
45 .pre_emp_bias = USB2_BIAS_28P15MV,
46 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
47 }" # Type-A Port 3
48 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
49 register "usb2_ports[4]" = "{
50 .enable = 1,
51 .ocpin = OC_SKIP,
52 .tx_bias = USB2_BIAS_0MV,
53 .tx_emp_enable = USB2_PRE_EMP_ON,
54 .pre_emp_bias = USB2_BIAS_28P15MV,
55 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
56 }" # Type-A Port 4
57 register "usb2_ports[5]" = "{
58 .enable = 1,
59 .ocpin = OC0,
60 .tx_bias = USB2_BIAS_0MV,
61 .tx_emp_enable = USB2_PRE_EMP_ON,
62 .pre_emp_bias = USB2_BIAS_28P15MV,
63 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
64 }" # Type-A port 0
65 register "usb2_ports[6]" = "USB2_PORT_EMPTY"
66 register "usb2_ports[7]" = "USB2_PORT_EMPTY"
67 register "usb2_ports[8]" = "USB2_PORT_EMPTY"
68 register "usb2_ports[9]" = "{
69 .enable = 1,
70 .ocpin = OC_SKIP,
71 .tx_bias = USB2_BIAS_0MV,
72 .tx_emp_enable = USB2_PRE_EMP_ON,
73 .pre_emp_bias = USB2_BIAS_28P15MV,
74 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
75 }" # BT
76
77 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2
78 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3
79 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1
80 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
81 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
82 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
83
84 # Bitmap for Wake Enable on USB attach/detach
85 register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
86 USB_PORT_WAKE_ENABLE(2) | \
87 USB_PORT_WAKE_ENABLE(3) | \
88 USB_PORT_WAKE_ENABLE(5) | \
89 USB_PORT_WAKE_ENABLE(6)"
90 register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
91 USB_PORT_WAKE_ENABLE(2) | \
92 USB_PORT_WAKE_ENABLE(3) | \
93 USB_PORT_WAKE_ENABLE(5) | \
94 USB_PORT_WAKE_ENABLE(6)"
95
96 # Enable eMMC HS400
97 register "ScsEmmcHs400Enabled" = "1"
98
99 # EMMC Tx CMD Delay
100 # Refer to EDS-Vol2-14.3.7.
101 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
102 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
103 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
104
105 # EMMC TX DATA Delay 1
106 # Refer to EDS-Vol2-14.3.8.
107 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
108 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
109 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911"
110
111 # EMMC TX DATA Delay 2
112 # Refer to EDS-Vol2-14.3.9.
113 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
114 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
115 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
116 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
117 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828"
118
119 # EMMC RX CMD/DATA Delay 1
120 # Refer to EDS-Vol2-14.3.10.
121 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
122 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
123 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
124 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
125 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b"
126
127 # EMMC RX CMD/DATA Delay 2
128 # Refer to EDS-Vol2-14.3.12.
129 # [17:16] stands for Rx Clock before Output Buffer,
130 # 00: Rx clock after output buffer,
131 # 01: Rx clock before output buffer,
132 # 10: Automatic selection based on working mode.
133 # 11: Reserved
134 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
135 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
136 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D"
137
138 # EMMC Rx Strobe Delay
139 # Refer to EDS-Vol2-14.3.11.
140 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
141 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
142 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"
143
144 # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them.
145 register "PchHdaAudioLinkSsp1" = "0"
146 register "PchHdaAudioLinkDmic0" = "0"
147
148 # Intel Common SoC Config
149 #+-------------------+---------------------------+
150 #| Field | Value |
151 #+-------------------+---------------------------+
152 #| GSPI0 | cr50 TPM. Early init is |
153 #| | required to set up a BAR |
154 #| | for TPM communication |
155 #| | before memory is up |
156 #| I2C0 | RFU |
157 #| I2C2 | PS175 |
158 #| I2C3 | MST |
159 #| I2C4 | Audio |
160 #+-------------------+---------------------------+
161 register "common_soc_config" = "{
162 .gspi[0] = {
163 .speed_mhz = 1,
164 .early_init = 1,
165 },
166 .i2c[0] = {
167 .speed = I2C_SPEED_FAST,
168 .rise_time_ns = 0,
169 .fall_time_ns = 0,
170 },
171 .i2c[2] = {
172 .speed = I2C_SPEED_FAST,
173 .rise_time_ns = 60,
174 .fall_time_ns = 60,
175 },
176 .i2c[3] = {
177 .speed = I2C_SPEED_FAST,
178 .rise_time_ns = 60,
179 .fall_time_ns = 60,
180 },
181 .i2c[4] = {
182 .speed = I2C_SPEED_FAST,
183 .rise_time_ns = 60,
184 .fall_time_ns = 60,
185 },
186 }"
187
188 # PCIe port 7 for LAN
189 register "PcieRpEnable[6]" = "1"
190 register "PcieRpLtrEnable[6]" = "1"
191 # PCIe port 11 (x2) for NVMe hybrid storage devices
192 register "PcieRpEnable[10]" = "1"
193 register "PcieRpLtrEnable[10]" = "1"
194 # Uses CLK SRC 0
195 register "PcieClkSrcUsage[0]" = "6"
196 register "PcieClkSrcClkReq[0]" = "0"
197
198 # GPIO for SD card detect
199 register "sdcard_cd_gpio" = "vSD3_CD_B"
200
201 # SATA port 1 Gen3 Strength
202 # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB
203 register "sata_port[1].TxGen3DeEmphEnable" = "1"
204 register "sata_port[1].TxGen3DeEmph" = "0x20"
205
206 device domain 0 on
207 device pci 14.0 on
208 chip drivers/usb/acpi
209 device usb 0.0 on
210 chip drivers/usb/acpi
211 register "desc" = ""USB2 Type-A Front Left""
212 register "type" = "UPC_TYPE_A"
213 register "group" = "ACPI_PLD_GROUP(0, 0)"
214 device usb 2.0 on end
215 end
216 chip drivers/usb/acpi
217 register "desc" = ""USB2 Type-C Port Rear""
218 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
219 register "group" = "ACPI_PLD_GROUP(1, 3)"
220 device usb 2.1 on end
221 end
222 chip drivers/usb/acpi
223 register "desc" = ""USB2 Type-A Front Right""
224 register "type" = "UPC_TYPE_A"
225 register "group" = "ACPI_PLD_GROUP(0, 1)"
226 device usb 2.2 on end
227 end
228 chip drivers/usb/acpi
229 register "desc" = ""USB2 Type-A Rear Right""
230 register "type" = "UPC_TYPE_A"
231 register "group" = "ACPI_PLD_GROUP(1, 2)"
232 device usb 2.3 on end
233 end
234 chip drivers/usb/acpi
235 register "desc" = ""USB2 Type-A Rear Middle""
236 register "type" = "UPC_TYPE_A"
237 register "group" = "ACPI_PLD_GROUP(1, 1)"
238 device usb 2.4 on end
239 end
240 chip drivers/usb/acpi
241 register "desc" = ""USB2 Type-A Rear Left""
242 register "type" = "UPC_TYPE_A"
243 register "group" = "ACPI_PLD_GROUP(1, 0)"
244 device usb 2.5 on end
245 end
246 chip drivers/usb/acpi
247 device usb 2.6 off end
248 end
249 chip drivers/usb/acpi
250 register "desc" = ""USB3 Type-A Front Left""
251 register "type" = "UPC_TYPE_USB3_A"
252 register "group" = "ACPI_PLD_GROUP(0, 0)"
253 device usb 3.0 on end
254 end
255 chip drivers/usb/acpi
256 register "desc" = ""USB3 Type-A Front Right""
257 register "type" = "UPC_TYPE_USB3_A"
258 register "group" = "ACPI_PLD_GROUP(0, 1)"
259 device usb 3.1 on end
260 end
261 chip drivers/usb/acpi
262 register "desc" = ""USB3 Type-A Rear Right""
263 register "type" = "UPC_TYPE_USB3_A"
264 register "group" = "ACPI_PLD_GROUP(1, 2)"
265 device usb 3.2 on end
266 end
267 chip drivers/usb/acpi
268 register "desc" = ""USB3 Type-C Rear""
269 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
270 register "group" = "ACPI_PLD_GROUP(1, 3)"
271 device usb 3.3 on end
272 end
273 chip drivers/usb/acpi
274 register "desc" = ""USB3 Type-A Rear Left""
275 register "type" = "UPC_TYPE_USB3_A"
276 register "group" = "ACPI_PLD_GROUP(1, 0)"
277 device usb 3.4 on end
278 end
279 chip drivers/usb/acpi
280 register "desc" = ""USB3 Type-A Rear Middle""
281 register "type" = "UPC_TYPE_USB3_A"
282 register "group" = "ACPI_PLD_GROUP(1, 1)"
283 device usb 3.5 on end
284 end
285 end
286 end
287 end # USB xHCI
288 device pci 15.0 off
289 # RFU - Reserved for Future Use.
290 end # I2C #0
291 device pci 15.1 off end # I2C #1
292 device pci 15.2 on
293 chip drivers/i2c/generic
294 register "hid" = ""1AF80175""
295 register "name" = ""PS17""
296 register "desc" = ""Parade PS175""
297 device i2c 4a on end
298 end
299 end # I2C #2, PCON PS175.
300 device pci 15.3 on
301 chip drivers/i2c/generic
302 register "hid" = ""10EC2142""
303 register "name" = ""RTD2""
304 register "desc" = ""Realtek RTD2142""
305 device i2c 4a on end
306 end
307 end # I2C #3, Realtek RTD2142.
308 device pci 19.0 on
309 chip drivers/i2c/generic
310 register "hid" = ""10EC5682""
311 register "name" = ""RT58""
312 register "desc" = ""Realtek RT5682""
313 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
314 register "property_count" = "1"
315 # Set the jd_src to RT5668_JD1 for jack detection
316 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
317 register "property_list[0].name" = ""realtek,jd-src""
318 register "property_list[0].integer" = "1"
319 device i2c 1a on end
320 end
321 end #I2C #4
322 device pci 1a.0 on end # eMMC
323 device pci 1c.6 on
324 chip drivers/net
325 register "customized_leds" = "0x05af"
326 register "wake" = "GPE0_DW1_07" # GPP_C7
327 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)"
328 register "stop_delay_ms" = "12" # NIC needs time to quiesce
329 register "stop_off_delay_ms" = "1"
330 register "has_power_resource" = "1"
331 register "device_index" = "0"
332 device pci 00.0 on end
333 end
334 end # RTL8111H Ethernet NIC
335 device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
336 device pci 1e.3 off end # GSPI #1
337 end
338
339 # VR Settings Configuration for 4 Domains
340 #+----------------+-------+-------+-------+-------+
341 #| Domain/Setting | SA | IA | GTUS | GTS |
342 #+----------------+-------+-------+-------+-------+
343 #| Psi1Threshold | 20A | 20A | 20A | 20A |
344 #| Psi2Threshold | 5A | 5A | 5A | 5A |
345 #| Psi3Threshold | 1A | 1A | 1A | 1A |
346 #| Psi3Enable | 1 | 1 | 1 | 1 |
347 #| Psi4Enable | 1 | 1 | 1 | 1 |
348 #| ImonSlope | 0 | 0 | 0 | 0 |
349 #| ImonOffset | 0 | 0 | 0 | 0 |
350 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
351 #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
352 #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
353 #+----------------+-------+-------+-------+-------+
354 #Note: IccMax settings are moved to SoC code
355 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
356 .vr_config_enable = 1,
357 .psi1threshold = VR_CFG_AMP(20),
358 .psi2threshold = VR_CFG_AMP(5),
359 .psi3threshold = VR_CFG_AMP(1),
360 .psi3enable = 1,
361 .psi4enable = 1,
362 .imon_slope = 0x0,
363 .imon_offset = 0x0,
364 .icc_max = 0,
365 .voltage_limit = 1520,
366 .ac_loadline = 1004,
367 .dc_loadline = 1004,
368 }"
369
370 register "domain_vr_config[VR_IA_CORE]" = "{
371 .vr_config_enable = 1,
372 .psi1threshold = VR_CFG_AMP(20),
373 .psi2threshold = VR_CFG_AMP(5),
374 .psi3threshold = VR_CFG_AMP(1),
375 .psi3enable = 1,
376 .psi4enable = 1,
377 .imon_slope = 0x0,
378 .imon_offset = 0x0,
379 .icc_max = 0,
380 .voltage_limit = 1520,
381 .ac_loadline = 181,
382 .dc_loadline = 181,
383 }"
384
385 register "domain_vr_config[VR_GT_UNSLICED]" = "{
386 .vr_config_enable = 1,
387 .psi1threshold = VR_CFG_AMP(20),
388 .psi2threshold = VR_CFG_AMP(5),
389 .psi3threshold = VR_CFG_AMP(1),
390 .psi3enable = 1,
391 .psi4enable = 1,
392 .imon_slope = 0x0,
393 .imon_offset = 0x0,
394 .icc_max = 0,
395 .voltage_limit = 1520,
396 .ac_loadline = 319,
397 .dc_loadline = 319,
398 }"
399
400 register "domain_vr_config[VR_GT_SLICED]" = "{
401 .vr_config_enable = 1,
402 .psi1threshold = VR_CFG_AMP(20),
403 .psi2threshold = VR_CFG_AMP(5),
404 .psi3threshold = VR_CFG_AMP(1),
405 .psi3enable = 1,
406 .psi4enable = 1,
407 .imon_slope = 0x0,
408 .imon_offset = 0x0,
409 .icc_max = 0,
410 .voltage_limit = 1520,
411 .ac_loadline = 319,
412 .dc_loadline = 319,
413 }"
414
415 end
ast, secure and flexible OpenSource firmware