util/msrtool/intel_core2_later.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include "msrtool.h"
   4
   5 int intel_core2_later_probe(const struct targetdef *target, const struct cpuid_t *id) {
   6         return ((VENDOR_INTEL == id->vendor) &&
   7                 (0x6 == id->family) &&
   8                 (0x17 == id->model));
   9 }
  10
  11 const struct msrdef intel_core2_later_msrs[] = {
  12         {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID Register",
  13                         "Model Specific Platform ID", {
  14         /* The OS can use this MSR to determine "slot" information for the
  15          * processor and the proper microcode update to load. */
  16                 { 63, 11, RESERVED },
  17                 { 52, 3, "Platform ID", "R/O", PRESENT_BIN, {
  18                         { MSR1(0), "Processor Flag 0" },
  19                         { MSR1(1), "Processor Flag 1" },
  20                         { MSR1(2), "Processor Flag 2" },
  21                         { MSR1(3), "Processor Flag 3" },
  22                         { MSR1(4), "Processor Flag 4" },
  23                         { MSR1(5), "Processor Flag 5" },
  24                         { MSR1(6), "Processor Flag 6" },
  25                         { MSR1(7), "Processor Flag 7" },
  26                         { BITVAL_EOT }
  27                 }},
  28                 { 49, 37, RESERVED },
  29                 { 12, 5, "Maximum Qualified Ratio:", "The maximum allowed bus ratio",
  30                                 PRESENT_DEC, {
  31                         { BITVAL_EOT }
  32                 }},
  33                 { 7, 8, RESERVED },
  34                 { BITS_EOT }
  35         }},
  36         { 0x2a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBL_CR_POWERON Register",
  37                         "Processor Hard Power-On Configuration", {
  38                 { 63, 41, RESERVED },
  39                 { 26, 5, "Integer Bus Frequency Ratio:", "R/O", PRESENT_DEC, {
  40                         { BITVAL_EOT }
  41                 }},
  42                 { 21, 2, "Symmetric Arbitration ID:", "R/O", PRESENT_BIN, {
  43                         { BITVAL_EOT }
  44                 }},
  45                 { 19, 1, RESERVED },
  46                 { 18, 1, "N/2:", "Non-integer bus ratio", PRESENT_DEC, {
  47                         { MSR1(0), "Integer ratio" },
  48                         { MSR1(1), "Non-integer ratio" },
  49                         { BITVAL_EOT }
  50                 }},
  51                 { 17, 2, "APIC Cluster ID:", "R/O", PRESENT_HEX, {
  52                         { BITVAL_EOT }
  53                 }},
  54                 { 15, 1, RESERVED },
  55                 { 14, 1, "1 Mbyte Power on Reset Vector", "R/O", PRESENT_DEC, {
  56                         { MSR1(0), "4 GBytes Power on Reset Vector" },
  57                         { MSR1(1), "1 Mbyte Power on Reset Vector" },
  58                         { BITVAL_EOT }
  59                 }},
  60                 { 13, 1, RESERVED },
  61                 { 12, 1, "BINIT# Observation", "R/O", PRESENT_DEC, {
  62                         { MSR1(0), "BINIT# Observation disabled" },
  63                         { MSR1(1), "BINIT# Observation enabled" },
  64                         { BITVAL_EOT }
  65                 }},
  66                 { 11, 1, "TXT", "Intel TXT Capable Chipset", PRESENT_DEC, {
  67                         { MSR1(0), "Intel TXT Capable Chipset not present" },
  68                         { MSR1(1), "Intel TXT Capable Chipset present" },
  69                         { BITVAL_EOT }
  70                 }},
  71                 { 10, 1, "MCERR# Observation:", "R/O", PRESENT_DEC, {
  72                         { MSR1(0), "MCERR# Observation disabled" },
  73                         { MSR1(1), "MCERR# Observation enabled" },
  74                         { BITVAL_EOT }
  75                 }},
  76                 { 9, 1, "Execute BIST", "R/O", PRESENT_DEC, {
  77                         { MSR1(0), "Execute BIST disabled" },
  78                         { MSR1(1), "Execute BIST enabled" },
  79                         { BITVAL_EOT }
  80                 }},
  81                 { 8, 1, "Output Tri-state", "R/O", PRESENT_DEC, {
  82                         { MSR1(0), "Output Tri-state disabled" },
  83                         { MSR1(1), "Output Tri-state enabled" },
  84                         { BITVAL_EOT }
  85                 }},
  86                 { 7, 1, "BINIT# Driver Enable", "R/W", PRESENT_DEC, {
  87                         { MSR1(0), "BINIT# Driver disabled" },
  88                         { MSR1(1), "BINIT# Driver enabled" },
  89                         { BITVAL_EOT }
  90                 }},
  91                 { 6, 2, RESERVED },
  92                 { 4, 1, "Address parity enable", "R/W", PRESENT_DEC, {
  93                         { MSR1(0), "Address parity disabled" },
  94                         { MSR1(1), "Address parity enabled" },
  95                         { BITVAL_EOT }
  96                 }},
  97                 { 3, 1, "MCERR# Driver Enable", "R/W", PRESENT_DEC, {
  98                         { MSR1(0), "MCERR# Driver disabled" },
  99                         { MSR1(1), "MCERR# Driver enabled" },
 100                         { BITVAL_EOT }
 101                 }},
 102                 { 2, 1, "Response error checking enable", "R/W", PRESENT_DEC, {
 103                         { MSR1(0), "Response Error Checking disabled" },
 104                         { MSR1(1), "Response Error Checking enabled" },
 105                         { BITVAL_EOT }
 106                 }},
 107                 { 1, 1, "Data error checking enable", "R/W", PRESENT_DEC, {
 108                         { MSR1(0), "Data error checking disabled" },
 109                         { MSR1(1), "Data error checking enabled" },
 110                         { BITVAL_EOT }
 111                 }},
 112                 { 0, 1, RESERVED },
 113                 { BITS_EOT }
 114         }},
 115         {0xcd, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_FSB_FREQ", "Scalable Bus Speed", {
 116         /* This field indicates the intended scalable bus clock speed */
 117                 { 63, 61, RESERVED },
 118                 { 2, 3, "Speed", "R/O", PRESENT_BIN, {
 119                         { MSR1(0), "267 MHz (FSB 1067)" },
 120                         { MSR1(1), "133 MHz (FSB 533)" },
 121                         { MSR1(2), "200 MHz (FSB 800)" },
 122                         { MSR1(3), "167 MHz (FSB 667)" },
 123                         { MSR1(4), "333 MHz (FSB 1333)" },
 124                         { MSR1(5), "100 MHz (FSB 400)" },
 125                         { MSR1(6), "400 MHz (FSB 1600)" },
 126                         { BITVAL_EOT }
 127                 }},
 128                 { BITS_EOT }
 129         }},
 130         {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BBL_CR_CTL3", "", {
 131                 { 63, 40, RESERVED },
 132                 { 23, 1, "L2 Present", "R/O", PRESENT_BIN, {
 133                         { MSR1(0), "L2 Present" },
 134                         { MSR1(1), "L2 Not Present" },
 135                         { BITVAL_EOT }
 136                 }},
 137                 { 22, 14, RESERVED },
 138                 { 8, 1, "L2 Enabled", "R/W", PRESENT_BIN, {
 139                 /* Until this bit is set the processor will not respond
 140                  * to the WBINVD instruction or the assertion
 141                  * of the FLUSH# input. */
 142                         { MSR1(0), "L2 is disabled" },
 143                         { MSR1(1), "L2 cache has been initialized" },
 144                         { BITVAL_EOT }
 145                 }},
 146                 { 7, 7, RESERVED},
 147                 { 0, 1, "L2 Hardware Enabled", "R/O", PRESENT_BIN, {
 148                         { MSR1(0), "L2 is hardware-disabled" },
 149                         { MSR1(1), "L2 is hardware-enabled" },
 150                         { BITVAL_EOT }
 151                 }},
 152                 { BITS_EOT }
 153         }},
 154         {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {
 155                 { BITS_EOT }
 156         }},
 157
 158         // Per core msrs
 159
 160         {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR",
 161                 "Pentium Processor Machine-Check Exception Address", {
 162                 { BITS_EOT }
 163         }},
 164         {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE",
 165                 "Pentium Processor Machine-Check Exception Type", {
 166                 { BITS_EOT }
 167         }},
 168         {0x6, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_SIZE", "", {
 169                 { BITS_EOT }
 170         }},
 171         {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STEP_COUNTER", "TSC", {
 172                 { BITS_EOT }
 173         }},
 174         {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "APIC BASE", {
 175                 /* In Intel's manual there is MAXPHYWID,
 176                  * which determine index of highest bit of
 177                  * APIC Base itself, so marking it as
 178                  * 'RESERVED'.
 179                  */
 180                 { 63, 52, RESERVED },
 181                 { 11, 1, "APIC Global Enable", "R/W", PRESENT_BIN, {
 182                         { BITVAL_EOT }
 183                 }},
 184                 { 10, 1, RESERVED },
 185                 { 9, 1, RESERVED },
 186                 { 8, 1, "BSP Flag", "R/W", PRESENT_BIN, {
 187                         { BITVAL_EOT }
 188                 }},
 189                 { 7, 8, RESERVED },
 190                 { BITS_EOT }
 191         }},
 192         {0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL",
 193                         "Control features in Intel 64Processor", {
 194                 { 63, 48, RESERVED },
 195                 /* if CPUID.01H: ECX[6] = 1 */
 196                 { 15, 1, "SENTER Global Enable", "R/WL", PRESENT_BIN, {
 197                         { MSR1(0), "SENTER leaf functions are disabled" },
 198                         { MSR1(1), "SENTER leaf functions are enabled" },
 199                         { BITVAL_EOT }
 200                 }},
 201                 /* if CPUID.01H: ECX[6] = 1 */
 202                 { 14, 7, "SENTER Local Function Enables", "R/WL", PRESENT_BIN, {
 203                         { BITVAL_EOT }
 204                 }},
 205                 { 7, 4, RESERVED },
 206                 { 3, 1, "SMRR Enable", "R/WL", PRESENT_BIN, {
 207                         { MSR1(0), "SMRR_PHYS_BASE and SMRR_PHYS_MASK are invisible in SMM" },
 208                         { MSR1(1), "SMRR_PHYS_BASE and SMRR_PHYS_MASK accessible from SMM" },
 209                         { BITVAL_EOT }
 210                 }},
 211                 /* if CPUID.01H: ECX[5 or 6] = 1 */
 212                 { 2, 1, "VMX outside of SMX operation", "R/WL", PRESENT_BIN, {
 213                         /* This bit enables VMX for system executive
 214                         * that do not require SMX.
 215                         */
 216                         { MSR1(0), "VMX outside of SMX operation disabled" },
 217                         { MSR1(1), "VMX outside of SMX operation enabled" },
 218                         { BITVAL_EOT }
 219                 }},
 220                 { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {
 221                         /* This bit enables a system executive to use
 222                          * VMX in conjunction with SMX to support Intel
 223                          * Trusted Execution Technology.
 224                          */
 225                         { MSR1(0), "VMX inside of SMX operation disabled" },
 226                         { MSR1(1), "VMX outside of SMX operation enabled" },
 227                         { BITVAL_EOT }
 228                 }},
 229                 /* if CPUID.01H: ECX[5 or 6] = 1 */
 230                 { 0, 1, "Lock bit", "R/WO", PRESENT_BIN, {
 231                         /* Once the Lock bit is set, the contents
 232                          * of this register cannot be modified.
 233                          * Therefore the lock bit must be set after
 234                          * configuring support for Intel Virtualization
 235                          * Technology and prior transferring control
 236                          * to an Option ROM or bootloader. Hence, once
 237                          * the lock bit is set, the entire IA32_FEATURE_CONTROL_MSR
 238                          * contents are preserved across RESET when
 239                          * PWRGOOD it not deasserted.
 240                          */
 241                         { MSR1(0), "IA32_FEATURE_CONTROL MSR can be modified" },
 242                         { MSR1(1), "IA32_FEATURE_CONTROL MSR cannot be modified" },
 243                         { BITVAL_EOT }
 244                 }},
 245                 { BITS_EOT }
 246         }},
 247         {0x40, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_FROM_IP", "", {
 248                 { BITS_EOT }
 249         }},
 250         {0x41, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_FROM_IP", "", {
 251                 { BITS_EOT }
 252         }},
 253         {0x42, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_FROM_IP", "", {
 254                 { BITS_EOT }
 255         }},
 256         {0x43, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_FROM_IP", "", {
 257                 { BITS_EOT }
 258         }},
 259         {0x60, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_TO_LIP", "", {
 260                 { BITS_EOT }
 261         }},
 262         {0x61, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_TO_LIP", "", {
 263                 { BITS_EOT }
 264         }},
 265         {0x62, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_TO_LIP", "", {
 266                 { BITS_EOT }
 267         }},
 268         {0x63, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_TO_LIP", "", {
 269                 { BITS_EOT }
 270         }},
 271         {0x79, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_UPDT_TRIG",
 272                         "BIOS Update Trigger Register (W)", {
 273                 { BITS_EOT }
 274         }},
 275         {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID",
 276                         "BIOS Update Signature ID (RO)", {
 277                 { BITS_EOT }
 278         }},
 279         {0xa0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SMRR_PHYS_BASE", "", {
 280                 { BITS_EOT }
 281         }},
 282         {0xa1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SMRR_PHYS_MASK", "", {
 283                 { BITS_EOT }
 284         }},
 285         {0xc1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC0", "", {
 286                 { BITS_EOT }
 287         }},
 288         {0xc2, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC1", "", {
 289                 { BITS_EOT }
 290         }},
 291         {0xe7, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MPERF", "", {
 292                 { BITS_EOT }
 293         }},
 294         {0xe8, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APERF", "", {
 295                 { BITS_EOT }
 296         }},
 297         {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", {
 298                 { 63, 52, RESERVED },
 299                 { 11, 1, "SMRR Capability Using MSR 0xa0 and 0xa1", "R/O", PRESENT_BIN, {
 300                         { BITVAL_EOT }
 301                 }},
 302                 { 10, 11, RESERVED },
 303                 { BITS_EOT }
 304         }},
 305         {0x174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", {
 306                 { BITS_EOT }
 307         }},
 308         {0x175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", {
 309                 { BITS_EOT }
 310         }},
 311         {0x176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", {
 312                 { BITS_EOT }
 313         }},
 314         {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", {
 315                 { BITS_EOT }
 316         }},
 317         {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", {
 318                 { 63, 61, RESERVED },
 319                 { 2, 1, "MCIP", "R/W", PRESENT_BIN, {
 320                         /* When set, bit indicates that a machine check has been
 321                          * generated. If a second machine check is detected while
 322                          * this bit is still set, the processor enters a shutdown state.
 323                          * Software should write this bit to 0 after processing
 324                          * a machine check exception.
 325                          */
 326                         { MSR1(0), "Nothing" },
 327                         { MSR1(1), "Machine check has been generated" },
 328                         { BITVAL_EOT }
 329                 }},
 330                 { 1, 1, "EPIV", "R/W", PRESENT_BIN, {
 331                         /* When set, bit indicates that the instruction addressed
 332                          * by the instruction pointer pushed on the stack (when
 333                          * the machine check was generated) is directly associated
 334                          * with the error
 335                          */
 336                         { MSR1(0), "Nothing" },
 337                         { MSR1(1), "Instruction addressed directly associated with the error" },
 338                         { BITVAL_EOT }
 339                 }},
 340                 { 0, 1, "RIPV", "R/W", PRESENT_BIN, {
 341                         /* When set, bit indicates that the instruction addressed
 342                          * by the instruction pointer pushed on the stack (when
 343                          * the machine check was generated) can be used to restart
 344                          * the program. If cleared, the program cannot be reliably restarted
 345                          */
 346                         { MSR1(0), "Program cannot be reliably restarted" },
 347                         { MSR1(1), "Instruction addressed can be used to restart the program" },
 348                         { BITVAL_EOT }
 349                 }},
 350                 { BITS_EOT }
 351         }},
 352         /* if CPUID.0AH: EAX[15:8] > 0 */
 353         {0x186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL0",
 354                         "Performance Event Select Register 0", {
 355                 { 63, 32, RESERVED },
 356                 { 31, 8, "CMASK", "R/W", PRESENT_HEX, {
 357                         /* When CMASK is not zero, the corresponding performance
 358                          * counter 0 increments each cycle if the event count
 359                          * is greater than or equal to the CMASK.
 360                          */
 361                         { BITVAL_EOT }
 362                 }},
 363                 { 23, 1, "INV", "R/W", PRESENT_BIN, {
 364                         { MSR1(0), "CMASK using as is" },
 365                         { MSR1(1), "CMASK inerting" },
 366                         { BITVAL_EOT }
 367                 }},
 368                 { 22, 1, "EN", "R/W", PRESENT_BIN, {
 369                         { MSR1(0), "No commence counting" },
 370                         { MSR1(1), "Commence counting" },
 371                         { BITVAL_EOT }
 372                 }},
 373                 { 21, 1, "AnyThread", "R/W", PRESENT_BIN, {
 374                         { BITVAL_EOT }
 375                 }},
 376                 { 20, 1, "INT", "R/W", PRESENT_BIN, {
 377                         { MSR1(0), "Interrupt on counter overflow is disabled" },
 378                         { MSR1(1), "Interrupt on counter overflow is enabled" },
 379                         { BITVAL_EOT }
 380                 }},
 381                 { 19, 1, "PC", "R/W", PRESENT_BIN, {
 382                         { MSR1(0), "Disabled pin control" },
 383                         { MSR1(1), "Enabled pin control" },
 384                         { BITVAL_EOT }
 385                 }},
 386                 { 18, 1, "Edge", "R/W", PRESENT_BIN, {
 387                         { MSR1(0), "Disabled edge detection" },
 388                         { MSR1(1), "Enabled edge detection" },
 389                         { BITVAL_EOT }
 390                 }},
 391                 { 17, 1, "OS", "R/W", PRESENT_BIN, {
 392                         { MSR1(0), "Nothing" },
 393                         { MSR1(1), "Counts while in privilege level is ring 0" },
 394                         { BITVAL_EOT }
 395                 }},
 396                 { 16, 1, "USR", "R/W", PRESENT_BIN, {
 397                         { MSR1(0), "Nothing" },
 398                         { MSR1(1), "Counts while in privilege level is not ring 0" },
 399                         { BITVAL_EOT }
 400                 }},
 401                 { 15, 8, "UMask", "R/W", PRESENT_HEX, {
 402                         /* Qualifies the microarchitectural condition
 403                          * to detect on the selected event logic. */
 404                         { BITVAL_EOT }
 405                 }},
 406                 { 7, 8, "Event Select", "R/W", PRESENT_HEX, {
 407                         /* Selects a performance event logic unit. */
 408                         { BITVAL_EOT }
 409                 }},
 410                 { BITS_EOT }
 411         }},
 412         /* if CPUID.0AH: EAX[15:8] > 0 */
 413         {0x187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL1",
 414                         "Performance Event Select Register 1", {
 415                 { 63, 32, RESERVED },
 416                 { 31, 8, "CMASK", "R/W", PRESENT_HEX, {
 417                         /* When CMASK is not zero, the corresponding performance
 418                          * counter 1 increments each cycle if the event count
 419                          * is greater than or equal to the CMASK.
 420                          */
 421                         { BITVAL_EOT }
 422                 }},
 423                 { 23, 1, "INV", "R/W", PRESENT_BIN, {
 424                         { MSR1(0), "CMASK using as is" },
 425                         { MSR1(1), "CMASK inerting" },
 426                         { BITVAL_EOT }
 427                 }},
 428                 { 22, 1, "EN", "R/W", PRESENT_BIN, {
 429                         { MSR1(0), "No commence counting" },
 430                         { MSR1(1), "Commence counting" },
 431                         { BITVAL_EOT }
 432                 }},
 433                 { 21, 1, "AnyThread", "R/W", PRESENT_BIN, {
 434                         { BITVAL_EOT }
 435                 }},
 436                 { 20, 1, "INT", "R/W", PRESENT_BIN, {
 437                         { MSR1(0), "Interrupt on counter overflow is disabled" },
 438                         { MSR1(1), "Interrupt on counter overflow is enabled" },
 439                         { BITVAL_EOT }
 440                 }},
 441                 { 19, 1, "PC", "R/W", PRESENT_BIN, {
 442                         { MSR1(0), "Disabled pin control" },
 443                         { MSR1(1), "Enabled pin control" },
 444                         { BITVAL_EOT }
 445                 }},
 446                 { 18, 1, "Edge", "R/W", PRESENT_BIN, {
 447                         { MSR1(0), "Disabled edge detection" },
 448                         { MSR1(1), "Enabled edge detection" },
 449                         { BITVAL_EOT }
 450                 }},
 451                 { 17, 1, "OS", "R/W", PRESENT_BIN, {
 452                         { MSR1(0), "Nothing" },
 453                         { MSR1(1), "Counts while in privilege level is ring 0" },
 454                         { BITVAL_EOT }
 455                 }},
 456                 { 16, 1, "USR", "R/W", PRESENT_BIN, {
 457                         { MSR1(0), "Nothing" },
 458                         { MSR1(1), "Counts while in privilege level is not ring 0" },
 459                         { BITVAL_EOT }
 460                 }},
 461                 { 15, 8, "UMask", "R/W", PRESENT_HEX, {
 462                         /* Qualifies the microarchitectural condition
 463                          * to detect on the selected event logic. */
 464                         { BITVAL_EOT }
 465                 }},
 466                 { 7, 8, "Event Select", "R/W", PRESENT_HEX, {
 467                         /* Selects a performance event logic unit. */
 468                         { BITVAL_EOT }
 469                 }},
 470                 { BITS_EOT }
 471         }},
 472         {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {
 473                 { BITS_EOT }
 474         }},
 475         {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CTL", "", {
 476                 { BITS_EOT }
 477         }},
 478         {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION",
 479                         "Clock Modulation", {
 480                 { 63, 59, RESERVED },
 481                 { 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN, {
 482                         { MSR1(0), "On demand Clock Modulation is disabled" },
 483                         { MSR1(1), "On demand Clock Modulation is enabled" },
 484                         { BITVAL_EOT }
 485                 }},
 486                 { 3, 3, "On demand Clock Modulation Duty Cycle", "R/W", PRESENT_HEX, {
 487                         { BITVAL_EOT }
 488                 }},
 489                 { 0, 1, RESERVED },
 490                 { BITS_EOT }
 491         }},
 492         {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT",
 493                         "Thermal Interrupt Control", {
 494                 { BITS_EOT }
 495         }},
 496         {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS",
 497                         "Thermal Monitor Status", {
 498                 { BITS_EOT }
 499         }},
 500         {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", {
 501                 { BITS_EOT }
 502         }},
 503         {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLE",
 504                         "Enable miscellaneous processor features", {
 505                 { 63, 24, RESERVED },
 506                 { 39, 1, "IP Prefetcher Disable", "R/W", PRESENT_BIN, {
 507                         { MSR1(0), "IP Prefetcher enabled" },
 508                         { MSR1(1), "IP Prefetcher disabled" },
 509                         { BITVAL_EOT }
 510                 }},
 511                 /* Note: [38] bit using for whole package,
 512                  * while some other bits can be Core or Thread
 513                  * specific.
 514                  */
 515                 { 38, 1, "IDA Disable", "R/W", PRESENT_BIN, {
 516                         /* When set to a 0 on processors that support IDA,
 517                          * CPUID.06H: EAX[1] reports the processor's
 518                          * support of turbo mode is enabled.
 519                          */
 520                         { MSR1(0), "IDA enabled" },
 521                         /* When set 1 on processors that support Intel Turbo Boost
 522                          * technology, the turbo mode feature is disabled and
 523                          * the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
 524                          */
 525                         { MSR1(1), "IDA disabled" },
 526                         { BITVAL_EOT }
 527                         /* Note: the power-on default value is used by BIOS to detect
 528                          * hardware support of turbo mode. If power-on default value is 1,
 529                          * turbo mode is available in the processor. If power-on default
 530                          * value is 0, turbo mode not available.
 531                          */
 532                 }},
 533                 { 37, 1, "DCU Prefetcher Disable", "R/W", PRESENT_BIN, {
 534                         { MSR1(0), "DCU L1 data cache prefetcher is enabled" },
 535                         { MSR1(1), "DCU L1 data cache prefetcher is disabled" },
 536                         { BITVAL_EOT }
 537                 }},
 538                 { 36, 2, RESERVED },
 539                 { 34, 1, "XD Bit Disable", "R/W", PRESENT_BIN, {
 540                         { BITVAL_EOT }
 541                 }},
 542                 { 33, 10, RESERVED },
 543                 { 23, 1, "xTPR Message Disable", "R/W", PRESENT_BIN, {
 544                         { BITVAL_EOT }
 545                 }},
 546                 { 22, 1, "Limit CPUID Maxval", "R/W", PRESENT_BIN, {
 547                         { BITVAL_EOT }
 548                 }},
 549                 { 21, 1, RESERVED },
 550                 { 20, 1, "Enhanced Intel SpeedStep Select Lock", "R/W",
 551                                 PRESENT_BIN, {
 552                         { MSR1(0), "Enhanced Intel SpeedStep Select "
 553                                 "and Enable bits are writeable" },
 554                         { MSR1(1), "Enhanced Intel SpeedStep Select "
 555                                 "and Enable bits are locked and R/O" },
 556                         { BITVAL_EOT }
 557                 }},
 558                 { 19, 1, "Adjacent Cache Line Prefetch Disable", "R/W",
 559                                 PRESENT_BIN, {
 560                         { MSR1(0), "Fetching cache lines that comprise a cache "
 561                                 "line pair (128 bytes)" },
 562                         { MSR1(1), "Fetching cache line that contains data "
 563                                 "currently required by the processor" },
 564                         { BITVAL_EOT }
 565                 }},
 566                 { 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN, {
 567                         { BITVAL_EOT }
 568                 }},
 569                 { 17, 1, "UNDOCUMENTED", "R/W", PRESENT_BIN, {
 570                         { BITVAL_EOT }
 571                 }},
 572                 /* Note: [16] bit using for whole package,
 573                  * while some other bits can be Core or Thread
 574                  * specific.
 575                  */
 576                 { 16, 1, "Enhanced Intel SpeedStep Technology Enable", "R/W",
 577                                 PRESENT_BIN, {
 578                         { BITVAL_EOT }
 579                 }},
 580                 { 15, 2, RESERVED },
 581                 { 13, 1, "TM2 Enable", "R/W", PRESENT_BIN, {
 582                         { BITVAL_EOT }
 583                 }},
 584                 { 12, 1, "Precise Event Based Sampling Unavailable", "R/O",
 585                                 PRESENT_BIN, {
 586                         { BITVAL_EOT }
 587                 }},
 588                 { 11, 1, "Branch Trace Storage Unavailable", "R/O", PRESENT_BIN, {
 589                         { BITVAL_EOT }
 590                 }},
 591                 { 10, 1, "FERR# Multiplexing Enable", "R/W", PRESENT_BIN, {
 592                         { MSR1(0), "FERR# signaling compatible behaviour" },
 593                         { MSR1(1), "FERR# asserted by the processor to indicate "
 594                                 "a pending break event within the processor" },
 595                         { BITVAL_EOT }
 596                 }},
 597                 { 9, 1, "Hardware Prefetcher Disable", "R/W", PRESENT_BIN, {
 598                         { MSR1(0), "Hardware prefetcher is enabled" },
 599                         { MSR1(1), "Hardware prefetcher is disabled" },
 600                         { BITVAL_EOT }
 601                 }},
 602                 { 8, 1, RESERVED },
 603                 { 7, 1, "Performance Monitoring Available", "R", PRESENT_BIN, {
 604                         { BITVAL_EOT }
 605                 }},
 606                 { 6, 3, RESERVED },
 607                 { 3, 1, "Automatic Thermal Control Circuit Enable", "R/W"
 608                                 , PRESENT_BIN, {
 609                         { BITVAL_EOT }
 610                 }},
 611                 { 2, 2, RESERVED },
 612                 { 0, 1, "Fast-Strings Enable", "R/W", PRESENT_BIN, {
 613                         { BITVAL_EOT }
 614                 }},
 615                 { BITS_EOT }
 616         }},
 617         {0x1c9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_TOS", "", {
 618                 { BITS_EOT }
 619         }},
 620         {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", {
 621                 { BITS_EOT }
 622         }},
 623         {0x1dd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_FROM_LIP", "", {
 624                 { BITS_EOT }
 625         }},
 626         {0x1de, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_TO_LIP", "", {
 627                 { BITS_EOT }
 628         }},
 629         {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE0", "", {
 630                 { BITS_EOT }
 631         }},
 632         {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK0", "", {
 633                 { BITS_EOT }
 634         }},
 635         {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE1", "", {
 636                 { BITS_EOT }
 637         }},
 638         {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK1", "", {
 639                 { BITS_EOT }
 640         }},
 641         {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE2", "", {
 642                 { BITS_EOT }
 643         }},
 644         {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK2", "", {
 645                 { BITS_EOT }
 646         }},
 647         {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE3", "", {
 648                 { BITS_EOT }
 649         }},
 650         {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK3", "", {
 651                 { BITS_EOT }
 652         }},
 653         {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE4", "", {
 654                 { BITS_EOT }
 655         }},
 656         {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK4", "", {
 657                 { BITS_EOT }
 658         }},
 659         {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE5", "", {
 660                 { BITS_EOT }
 661         }},
 662         {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK5", "", {
 663                 { BITS_EOT }
 664         }},
 665         {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE6", "", {
 666                 { BITS_EOT }
 667         }},
 668         {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK6", "", {
 669                 { BITS_EOT }
 670         }},
 671         {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE7", "", {
 672                 { BITS_EOT }
 673         }},
 674         {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK7", "", {
 675                 { BITS_EOT }
 676         }},
 677         {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", {
 678                 { BITS_EOT }
 679         }},
 680         {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", {
 681                 { BITS_EOT }
 682         }},
 683         {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", {
 684                 { BITS_EOT }
 685         }},
 686         {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", {
 687                 { BITS_EOT }
 688         }},
 689         {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", {
 690                 { BITS_EOT }
 691         }},
 692         {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", {
 693                 { BITS_EOT }
 694         }},
 695         {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", {
 696                 { BITS_EOT }
 697         }},
 698         {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", {
 699                 { BITS_EOT }
 700         }},
 701         {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", {
 702                 { BITS_EOT }
 703         }},
 704         {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", {
 705                 { BITS_EOT }
 706         }},
 707         {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", {
 708                 { BITS_EOT }
 709         }},
 710         {0x277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "IA32_PAT", {
 711                 { 63, 5, RESERVED },
 712                 { 58, 3, "PA7", "R/W", PRESENT_BIN, {
 713                         { BITVAL_EOT }
 714                 }},
 715                 { 55, 5, RESERVED },
 716                 { 40, 3, "PA6", "R/W", PRESENT_BIN, {
 717                         { BITVAL_EOT }
 718                 }},
 719                 { 47, 5, RESERVED },
 720                 { 42, 3, "PA5", "R/W", PRESENT_BIN, {
 721                         { BITVAL_EOT }
 722                 }},
 723                 { 39, 5, RESERVED },
 724                 { 34, 3, "PA4", "R/W", PRESENT_BIN, {
 725                         { BITVAL_EOT }
 726                 }},
 727                 { 31, 5, RESERVED },
 728                 { 26, 3, "PA3", "R/W", PRESENT_BIN, {
 729                         { BITVAL_EOT }
 730                 }},
 731                 { 23, 5, RESERVED },
 732                 { 18, 3, "PA2", "R/W", PRESENT_BIN, {
 733                         { BITVAL_EOT }
 734                 }},
 735                 { 15, 5, RESERVED },
 736                 { 10, 3, "PA1", "R/W", PRESENT_BIN, {
 737                         { BITVAL_EOT }
 738                 }},
 739                 { 7, 5, RESERVED },
 740                 { 2, 3, "PA0", "R/W", PRESENT_BIN, {
 741                         { BITVAL_EOT }
 742                 }},
 743                 { BITS_EOT }
 744         }},
 745         {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE",
 746                         "Default Memory Types", {
 747                 { 63, 52, RESERVED },
 748                 { 11, 1, "MTRR Enable", "R/W", PRESENT_BIN, {
 749                         { BITVAL_EOT }
 750                 }},
 751                 { 10, 1, "Fixed Range MTRR Enable", "R/W", PRESENT_BIN, {
 752                         { BITVAL_EOT }
 753                 }},
 754                 { 9, 7, RESERVED },
 755                 { 2, 3, "Default Memory Type", "R/W", PRESENT_HEX, {
 756                         { BITVAL_EOT }
 757                 }},
 758                 { BITS_EOT }
 759         }},
 760         /* if CPUID.0AH: EDX[4:0] > 0 */
 761         {0x309, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR0", "Fixed-Function "
 762                         "Performance Counter Register 0: Counts Instr_Retired.Any", {
 763                 /* Also known as MSR_PERF_FIXED_CTR0 */
 764                 { BITS_EOT }
 765         }},
 766         /* if CPUID.0AH: EDX[4:0] > 1 */
 767         {0x30a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR1", "Fixed-Function "
 768                         "Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", {
 769                 /* Also known as MSR_PERF_FIXED_CTR1 */
 770                 { BITS_EOT }
 771         }},
 772         /* if CPUID.0AH: EDX[4:0] > 2 */
 773         {0x30b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR2", "Fixed-Function "
 774                         "Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", {
 775                 /* Also known as MSR_PERF_FIXED_CTR2 */
 776                 { BITS_EOT }
 777         }},
 778         {0x345, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_CAPABILITIES", "", {
 779         /* Additional info available at Section 17.4.1 of
 780          * Intel 64 and IA-32 Architectures Software Developer's
 781          * Manual, Volume 3.
 782          */
 783                 { 63, 56, RESERVED },
 784                 { 7, 1, "PEBSSaveArchRegs", "R/O", PRESENT_BIN, {
 785                         { BITVAL_EOT }
 786                 }},
 787                 { 6, 1, "PEBS Record Format", "R/O", PRESENT_BIN, {
 788                         { BITVAL_EOT }
 789                 }},
 790                 { 5, 6, "LBR Format", "R/O", PRESENT_HEX, {
 791                         { BITVAL_EOT }
 792                 }},
 793                 { BITS_EOT }
 794         }},
 795         /* if CPUID.0AH: EAX[7:0] > 1*/
 796         {0x38d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR_CTRL",
 797                 "Fixed-Function-Counter Control Register", {
 798         /* Also known as MSR_PERF_FIXED_CTR_CTRL.
 799          * Counter increments while the results of ANDing respective enable bit
 800          * in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits
 801          * in this MSR is true. */
 802                 { 63, 52, RESERVED },
 803                 { 11, 1, "EN2_PMI", "R/W", PRESENT_BIN, {
 804                         { MSR1(0), "Nothing" },
 805                         { MSR1(1), "PMI when fixed counter 2 overflows is enabled" },
 806                         { BITVAL_EOT }
 807                 }},
 808                 /* if CPUID.0AH EAX[7:0] > 2 */
 809                 { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
 810                         { MSR1(0), "Counter only increments the associated event "
 811                                 "conditions occurring in the logical processor "
 812                                 "which programmed the MSR" },
 813                         { MSR1(1), "Counting the associated event conditions "
 814                                 "occurring across all logical processors sharing "
 815                                 "a processor core" },
 816                         { BITVAL_EOT }
 817                 }},
 818                 { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
 819                         { MSR1(0), "Nothing" },
 820                         { MSR1(1), "Fixed counter 2 is enabled to count while CPL > 0" },
 821                         { BITVAL_EOT }
 822                 }},
 823                 { 8, 1, "EN2_OS", "R/W", PRESENT_BIN, {
 824                         { MSR1(0), "Nothing" },
 825                         { MSR1(1), "Fixed counter 2 is enabled to count while CPL = 0" },
 826                         { BITVAL_EOT }
 827                 }},
 828                 { 7, 1, "EN1_PMI", "R/W", PRESENT_BIN, {
 829                         { MSR1(0), "Nothing" },
 830                         { MSR1(1), "PMI when fixed counter 1 overflows is enabled" },
 831                         { BITVAL_EOT }
 832                 }},
 833                 /* if CPUID.0AH: EAX[7:0] > 2 */
 834                 { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
 835                         { MSR1(0), "Counter only increments the associated event "
 836                                 "conditions occurring in the logical processor "
 837                                 "which programmed the MSR" },
 838                         { MSR1(1), "Counting the associated event conditions "
 839                                 "occurring across all logical processors sharing "
 840                                 "a processor core" },
 841                         { BITVAL_EOT }
 842                 }},
 843                 { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
 844                         { MSR1(0), "Nothing" },
 845                         { MSR1(1), "Fixed counter 1 is enabled to count while CPL > 0" },
 846                         { BITVAL_EOT }
 847                 }},
 848                 { 4, 1, "EN1_OS", "R/W", PRESENT_BIN, {
 849                         { MSR1(0), "Nothing" },
 850                         { MSR1(1), "Fixed counter 1 is enabled to count while CPL = 0" },
 851                         { BITVAL_EOT }
 852                 }},
 853                 { 3, 1, "EN0_PMI", "R/W", PRESENT_BIN, {
 854                         { MSR1(0), "Nothing" },
 855                         { MSR1(1), "PMI when fixed counter 0 overflows is enabled" },
 856                         { BITVAL_EOT }
 857                 }},
 858                 /* if CPUID.0AH: EAX[7:0] > 2 */
 859                 { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
 860                         { MSR1(0), "Counter only increments the associated event "
 861                                 "conditions occurring in the logical processor "
 862                                 "which programmed the MSR" },
 863                         { MSR1(1), "Counting the associated event conditions "
 864                                 "occurring across all logical processors sharing "
 865                                 "a processor core" },
 866                         { BITVAL_EOT }
 867                 }},
 868                 { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
 869                         { MSR1(0), "Nothing" },
 870                         { MSR1(1), "Fixed counter 0 is enabled to count while CPL > 0" },
 871                         { BITVAL_EOT }
 872                 }},
 873                 { 0, 1, "EN0_OS", "R/W", PRESENT_BIN, {
 874                         { MSR1(0), "Nothing" },
 875                         { MSR1(1), "Fixed counter 0 is enabled to count while CPL = 0" },
 876                         { BITVAL_EOT }
 877                 }},
 878                 { BITS_EOT }
 879         }},
 880         /* if CPUID.0AH: EAX[7:0] > 0 */
 881         {0x38e, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_GLOBAL_STATUS",
 882                         "Global Performance Counter Status", {
 883         /* Also known as MSR_PERF_GLOBAL_STATUS */
 884                 /* if CPUID.0AH: EAX[7:0] > 0 */
 885                 { 63, 1, "CondChg: Status bits of this register has changed",
 886                                 "R/O", PRESENT_BIN, {
 887                         { BITVAL_EOT }
 888                 }},
 889                 /* if CPUID.0AH: EAX[7:0] > 0 */
 890                 { 62, 1, "OvfBuf: DS SAVE area Buffer overflow status",
 891                                 "R/O", PRESENT_BIN, {
 892                         { BITVAL_EOT }
 893                 }},
 894                 /* if CPUID.0AH: EAX[7:0] > 2 */
 895                 { 61, 1, "Ovf_Uncore: Uncore counter overflow status",
 896                                 "R/O", PRESENT_BIN, {
 897                         { BITVAL_EOT }
 898                 }},
 899                 { 60, 26, RESERVED },
 900                 /* if CPUID.0AH: EAX[7:0] > 1 */
 901                 { 34, 1, "Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2",
 902                                 "R/O", PRESENT_BIN, {
 903                         { BITVAL_EOT }
 904                 }},
 905                 /* if CPUID.0AH: EAX[7:0] > 1 */
 906                 { 33, 1, "Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1",
 907                                 "R/O", PRESENT_BIN, {
 908                         { BITVAL_EOT }
 909                 }},
 910                 /* if CPUID.0AH: EAX[7:0] > 1 */
 911                 { 32, 1, "Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0",
 912                                 "R/O", PRESENT_BIN, {
 913                         { BITVAL_EOT }
 914                 }},
 915                 { 31, 28, RESERVED },
 916                 /* presented only in 06_2EH Nehalem model */
 917                 { 3, 1, "Ovf_PMC3: Overflow status of IA32_PMC3", "R/O", PRESENT_BIN, {
 918                         { BITVAL_EOT }
 919                 }},
 920                 /* presented only in 06_2EH Nehalem model */
 921                 { 2, 1, "Ovf_PMC2: Overflow status of IA32_PMC2", "R/O", PRESENT_BIN, {
 922                         { BITVAL_EOT }
 923                 }},
 924                 /* if CPUID.0AH: EAX[7:0] > 0 */
 925                 { 1, 1, "Ovf_PMC1: Overflow status of IA32_PMC1", "R/O", PRESENT_BIN, {
 926                         { BITVAL_EOT }
 927                 }},
 928                 /* if CPUID.0AH: EAX[7:0] > 0 */
 929                 { 0, 1, "Ovf_PMC0: Overflow status of IA32_PMC0", "R/O", PRESENT_BIN, {
 930                         { BITVAL_EOT }
 931                 }},
 932                 { BITS_EOT }
 933         }},
 934         /* if CPUID.0AH: EAX[7:0] > 0 */
 935         {0x38f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_CTL",
 936                 "Global Performance Counter Control", {
 937         /* Counter increments while the result of ANDing respective
 938          * enable bit in this MSR with corresponding OS or USR bits
 939          * in general-purpose or fixed counter control MSR is true.
 940          */
 941                 { 63, 29, RESERVED },
 942                 /* if CPUID.0AH: EAX[7:0] > 1 */
 943                 { 34, 1, "EN_FIXED_CTR2", "R/W", PRESENT_BIN, {
 944                         { BITVAL_EOT }
 945                 }},
 946                 /* if CPUID.0AH: EAX[7:0] > 1 */
 947                 { 33, 1, "EN_FIXED_CTR1", "R/W", PRESENT_BIN, {
 948                         { BITVAL_EOT }
 949                 }},
 950                 /* if CPUID.0AH: EAX[7:0] > 1 */
 951                 { 32, 1, "EN_FIXED_CTR0", "R/W", PRESENT_BIN, {
 952                         { BITVAL_EOT }
 953                 }},
 954                 { 31, 30, RESERVED },
 955                 /* if CPUID.0AH: EAX[7:0] > 0 */
 956                 { 1, 1, "EN_PMC1", "R/W", PRESENT_BIN, {
 957                         { BITVAL_EOT }
 958                 }},
 959                 /* if CPUID.0AH: EAX[7:0] > 0 */
 960                 { 0, 1, "EN_PMC0", "R/W", PRESENT_BIN, {
 961                         { BITVAL_EOT }
 962                 }},
 963                 { BITS_EOT }
 964         }},
 965         /* if CPUID.0AH: EAX[7:0] > 0 */
 966         {0x390, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_OVF_CTL",
 967                         "Global Performance Counter Overflow Control", {
 968                 /* if CPUID.0AH: EAX[7:0] > 0 */
 969                 { 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN, {
 970                         { BITVAL_EOT }
 971                 }},
 972                 /* if CPUID.0AH: EAX[7:0] > 0 */
 973                 { 62, 1, "Clear OvfBuf bit", "R/W", PRESENT_BIN, {
 974                         { BITVAL_EOT }
 975                 }},
 976                 /* Presented only in 06_2EH Nehalem model */
 977                 { 61, 1, "Clear Ovf_Uncore bit", "R/W", PRESENT_BIN, {
 978                         { BITVAL_EOT }
 979                 }},
 980                 { 60, 26, RESERVED },
 981                 /* if CPUID.0AH: EAX[7:0] > 1 */
 982                 { 34, 1, "Clear Ovf_FIXED_CTR2 bit", "R/W", PRESENT_BIN, {
 983                         { BITVAL_EOT }
 984                 }},
 985                 /* if CPUID.0AH: EAX[7:0] > 1 */
 986                 { 33, 1, "Clear Ovf_FIXED_CTR1 bit", "R/W", PRESENT_BIN, {
 987                         { BITVAL_EOT }
 988                 }},
 989                 /* if CPUID.0AH: EAX[7:0] > 1 */
 990                 { 32, 1, "Clear Ovf_FIXED_CTR0 bit", "R/W", PRESENT_BIN, {
 991                         { BITVAL_EOT }
 992                 }},
 993                 { 31, 30, RESERVED },
 994                 /* if CPUID.0AH: EAX[7:0] > 0 */
 995                 { 1, 1, "Clear Ovf_PMC1 bit", "R/W", PRESENT_BIN, {
 996                         { BITVAL_EOT }
 997                 }},
 998                 /* if CPUID.0AH: EAX[7:0] > 0 */
 999                 { 0, 1, "Clear Ovf_PMC0 bit", "R/W", PRESENT_BIN, {
1000                         { BITVAL_EOT }
1001                 }},
1002                 { BITS_EOT }
1003         }},
1004         /* See Section 18.6.1.1 of Intel 64 and IA-32 Architectures
1005          * Software Developer's Manual, Volume 3,
1006          * "Precise Event Based Sampling (PEBS)".
1007          */
1008         {0x3f1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PEBS_ENABLE", "PEBS Control", {
1009                 { 63, 28, RESERVED },
1010                 { 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN, {
1011                         { MSR1(0), "Disabled" },
1012                         { MSR1(1), "Enabled" },
1013                         { BITVAL_EOT }
1014                 }},
1015                 { 34, 1, "Load Latency on IA32_PMC2", "R/W", PRESENT_BIN, {
1016                         { MSR1(0), "Disabled" },
1017                         { MSR1(1), "Enabled" },
1018                         { BITVAL_EOT }
1019                 }},
1020                 { 33, 1, "Load Latency on IA32_PMC1", "R/W", PRESENT_BIN, {
1021                         { MSR1(0), "Disabled" },
1022                         { MSR1(1), "Enabled" },
1023                         { BITVAL_EOT }
1024                 }},
1025                 { 32, 1, "Load Latency on IA32_PMC0", "R/W", PRESENT_BIN, {
1026                         { MSR1(0), "Disabled" },
1027                         { MSR1(1), "Enabled" },
1028                         { BITVAL_EOT }
1029                 }},
1030                 { 31, 28, RESERVED },
1031                 { 3, 1, "PEBS on IA32_PMC3", "R/W", PRESENT_BIN, {
1032                         { MSR1(0), "Disabled" },
1033                         { MSR1(1), "Enabled" },
1034                         { BITVAL_EOT }
1035                 }},
1036                 { 2, 1, "PEBS on IA32_PMC2", "R/W", PRESENT_BIN, {
1037                         { MSR1(0), "Disabled" },
1038                         { MSR1(1), "Enabled" },
1039                         { BITVAL_EOT }
1040                 }},
1041                 { 1, 1, "PEBS on IA32_PMC1", "R/W", PRESENT_BIN, {
1042                         { MSR1(0), "Disabled" },
1043                         { MSR1(1), "Enabled" },
1044                         { BITVAL_EOT }
1045                 }},
1046                 { 0, 1, "PEBS on IA32_PMC0", "R/W", PRESENT_BIN, {
1047                         { MSR1(0), "Disabled" },
1048                         { MSR1(1), "Enabled" },
1049                         { BITVAL_EOT }
1050                 }},
1051                 { BITS_EOT }
1052         }},
1053         {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", {
1054                 { BITS_EOT }
1055         }},
1056         {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", {
1057                 { BITS_EOT }
1058         }},
1059         {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", {
1060                 { BITS_EOT }
1061         }},
1062         {0x403, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_MISC", "", {
1063                 { BITS_EOT }
1064         }},
1065         {0x404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", {
1066                 { BITS_EOT }
1067         }},
1068         {0x405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", {
1069                 { BITS_EOT }
1070         }},
1071         {0x406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", {
1072                 { BITS_EOT }
1073         }},
1074         {0x407, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_MISC", "", {
1075                 { BITS_EOT }
1076         }},
1077         {0x408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", {
1078                 { BITS_EOT }
1079         }},
1080         {0x409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", {
1081                 { BITS_EOT }
1082         }},
1083         {0x40a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_ADDR", "", {
1084                 { BITS_EOT }
1085         }},
1086         {0x40b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_MISC", "", {
1087                 { BITS_EOT }
1088         }},
1089         {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", {
1090                 { BITS_EOT }
1091         }},
1092         {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", {
1093                 { BITS_EOT }
1094         }},
1095         {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", {
1096                 { BITS_EOT }
1097         }},
1098         {0x40f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_MISC", "", {
1099                 { BITS_EOT }
1100         }},
1101         {0x410, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL", "", {
1102                 { BITS_EOT }
1103         }},
1104         {0x411, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", {
1105                 { BITS_EOT }
1106         }},
1107         {0x412, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_ADDR", "", {
1108                 { BITS_EOT }
1109         }},
1110         {0x413, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_MISC", "", {
1111                 { BITS_EOT }
1112         }},
1113         {0x414, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_CTL", "", {
1114                 { BITS_EOT }
1115         }},
1116         {0x415, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_STATUS", "", {
1117                 { BITS_EOT }
1118         }},
1119         {0x416, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_ADDR", "", {
1120                 { BITS_EOT }
1121         }},
1122         {0x417, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_MISC", "", {
1123                 { BITS_EOT }
1124         }},
1125         {0x418, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_CTL", "", {
1126                 { BITS_EOT }
1127         }},
1128         {0x419, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_STATUS", "", {
1129                 { BITS_EOT }
1130         }},
1131         {0x480, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_BASIC",
1132                         "Reporting Register of Basic VMX Capabilities", {
1133                 /* Additional info available at
1134                  * Appendix A.1, "Basic VMX Information" */
1135                 { 63, 10, RESERVED },
1136                 { 53, 4, "Memory type for VMREAD and VMWRITE", "R/O", PRESENT_HEX, {
1137                         { BITVAL_EOT }
1138                 }},
1139                 { 49, 1, "Support of dual-treatment of system-management functions",
1140                                 "R/O", PRESENT_BIN, {
1141                         { BITVAL_EOT }
1142                 }},
1143                 { 48, 1, "Enable full linear address access", "R/O", PRESENT_BIN, {
1144                         { BITVAL_EOT }
1145                 }},
1146                 { 47, 3, RESERVED },
1147                 { 44, 13, "VMXON region allocation size", "R/O", PRESENT_DEC, {
1148                         { BITVAL_EOT }
1149                 }},
1150                 { 31, 32, "VMCS Revision Identifier", "R/O", PRESENT_HEX, {
1151                         { BITVAL_EOT }
1152                 }},
1153                 { BITS_EOT }
1154         }},
1155         {0x481, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PINBASED_CTLS",
1156                         "Capability Reporting Register of "
1157                         "Pin-based VM-execution Controls", {
1158                 /* Additional info available at Appendix A.3,
1159                  * "VM-Execution Controls" */
1160                 { BITS_EOT }
1161         }},
1162         {0x482, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PROCBASED_CTLS",
1163                         "Capability Reporting Register of "
1164                         "Primary Processor-based VM-execution Controls", {
1165                 /* Additional info available at Appendix A.3,
1166                  * "VM-Execution Controls" */
1167                 { BITS_EOT }
1168         }},
1169         {0x483, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_EXIT_CTLS",
1170                         "Capability Reporting Register of VM-exit Controls", {
1171                 /* Additional info available at Appendix A.4,
1172                  * "VM-Exit Controls" */
1173                 { BITS_EOT }
1174         }},
1175         {0x484, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_ENTRY_CTLS",
1176                         "Capability Reporting Register of VM-entry Controls", {
1177                 /* Additional info available at Appendix A.5,
1178                  * "VM-Entry Controls" */
1179                 { BITS_EOT }
1180         }},
1181         {0x485, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_MISC",
1182                         "Reporting Register of Miscellaneous VMX Capabilities", {
1183                 /* Additional info available at Appendix A.6,
1184                  * "Miscellaneous Data" */
1185                 { BITS_EOT }
1186         }},
1187         {0x486, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED0",
1188                         "Capability Reporting Register of CR0 Bits Fixed to 0", {
1189                 /* Additional info available at Appendix A.7,
1190                  * "VMX-Fixed Bits in CR0" */
1191                 { BITS_EOT }
1192         }},
1193         {0x487, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED1",
1194                         "Capability Reporting Register of CR0 Bits Fixed to 1", {
1195                 /* Additional info available at Appendix A.7,
1196                  * "VMX-Fixed Bits in CR0" */
1197                 { BITS_EOT }
1198         }},
1199         {0x488, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED0",
1200                         "Capability Reporting Register of CR4 Bits Fixed to 0", {
1201                 /* Additional info available at Appendix A.8,
1202                  * "VMX-Fixed Bits in CR4" */
1203                 { BITS_EOT }
1204         }},
1205         {0x489, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED1",
1206                         "Capability Reporting Register of CR4 Bits Fixed to 1", {
1207                 /* Additional info available at Appendix A.8,
1208                  * "VMX-Fixed Bits in CR4" */
1209                 { BITS_EOT }
1210         }},
1211         {0x48a, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_VMCS_ENUM",
1212                         "Capability Reporting Register of VMCS Field Enumeration", {
1213                 /* Additional info available at Appendix A.9,
1214                  * "VMCS Enumeration" */
1215                 { BITS_EOT }
1216         }},
1217         {0x48b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2",
1218                         "Capability Reporting Register of Secondary "
1219                         "Processor-based VM-execution Controls", {
1220                 /* Additional info available at Appendix A.3,
1221                  * "VM-Execution Controls" */
1222                 { BITS_EOT }
1223         }},
1224         {0x600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "DS Save Area", {
1225                 /* Additional info available at Section 18.10.4 of Intel 64
1226                  * and IA-32 Architectures Software Developer's Manual,
1227                  * "Debug Store (DS) Mechanism".
1228                  */
1229                 { 63, 32, RESERVED }, // reserved if not in IA-32e mode
1230                 { 31, 32, "Linear address of DS buffer management area",
1231                                 "R/W", PRESENT_HEX, {
1232                         { BITVAL_EOT }
1233                 }},
1234                 { BITS_EOT }
1235         }},
1236         {0x107cc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL0", "", {
1237                 { BITS_EOT }
1238         }},
1239         {0x107cd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL1", "", {
1240                 { BITS_EOT }
1241         }},
1242         {0x107ce, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL2", "", {
1243                 { BITS_EOT }
1244         }},
1245         {0x107cf, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL3", "", {
1246                 { BITS_EOT }
1247         }},
1248         {0x107d0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL4", "", {
1249                 { BITS_EOT }
1250         }},
1251         {0x107d1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL5", "", {
1252                 { BITS_EOT }
1253         }},
1254         {0x107d2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL6", "", {
1255                 { BITS_EOT }
1256         }},
1257         {0x107d3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL7", "", {
1258                 { BITS_EOT }
1259         }},
1260         {0x107d8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_GL_CTL", "", {
1261                 { BITS_EOT }
1262         }},
1263         {0xc0000080, MSRTYPE_RDWR, MSR2(0, 0), "IA32_EFER", "", {
1264                 { BITS_EOT }
1265         }},
1266         {0xc0000081, MSRTYPE_RDWR, MSR2(0, 0), "IA32_STAR", "", {
1267                 { BITS_EOT }
1268         }},
1269         {0xc0000082, MSRTYPE_RDWR, MSR2(0, 0), "IA32_LSTAR", "", {
1270                 { BITS_EOT }
1271         }},
1272         {0xc0000084, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FMASK", "", {
1273                 { BITS_EOT }
1274         }},
1275         {0xc0000100, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FS_BASE", "", {
1276                 { BITS_EOT }
1277         }},
1278         {0xc0000101, MSRTYPE_RDWR, MSR2(0, 0), "IA32_GS_BASE", "", {
1279                 { BITS_EOT }
1280         }},
1281         {0xc0000102, MSRTYPE_RDWR, MSR2(0, 0), "IA32_KERNEL_GS_BASE", "", {
1282                 { BITS_EOT }
1283         }},
1284         { MSR_EOT }
1285 };