src/mainboard/prodrive/hermes/devicetree.cb

   1 chip soc/intel/cannonlake
   2         # FSP configuration
   3
   4         register "SataSalpSupport" = "0"
   5         register "satapwroptimize" = "1"
   6         register "SataPortsDevSlp[1]" = "1"     # PCH_M2_SATA_DEVSLP1
   7
   8         register "SataPortsEnable[0]" = "1"
   9         register "SataPortsEnable[1]" = "1"     # depends on SATAXPCIE1
  10         register "SataPortsEnable[2]" = "0"     # Not used for SATA
  11         register "SataPortsEnable[3]" = "0"     # Not used for SATA
  12         register "SataPortsEnable[4]" = "1"
  13         register "SataPortsEnable[5]" = "1"
  14         register "SataPortsEnable[6]" = "1"
  15         register "SataPortsEnable[7]" = "1"
  16
  17         register "SataPortsHotPlug[0]" = "1"
  18         register "SataPortsHotPlug[1]" = "1"
  19         register "SataPortsHotPlug[2]" = "0"
  20         register "SataPortsHotPlug[3]" = "0"
  21         register "SataPortsHotPlug[4]" = "1"
  22         register "SataPortsHotPlug[5]" = "1"
  23         register "SataPortsHotPlug[6]" = "1"
  24         register "SataPortsHotPlug[7]" = "1"
  25
  26         register "PchHdaDspEnable" = "0"
  27         register "PchHdaAudioLinkHda" = "1"
  28
  29         register "PcieClkSrcUsage[0]" = "20"            # PCIe Slot1
  30         register "PcieClkSrcUsage[1]" = "0x40"          # PCIe Slot2
  31         register "PcieClkSrcUsage[2]" = "0x42"          # PCIe Slot4
  32         register "PcieClkSrcUsage[3]" = "0x41"          # PCIe Slot6
  33         register "PcieClkSrcUsage[4]" = "8"             # RP9 M2 Slot M x4
  34         register "PcieClkSrcUsage[5]" = "15"            # RP16 M2 Slot E x1
  35         register "PcieClkSrcUsage[6]" = "14"            # BMC
  36         register "PcieClkSrcUsage[7]" = "4"             # PHY 3
  37         register "PcieClkSrcUsage[8]" = "PCIE_CLK_RP0"  # PCIe Slot3
  38         register "PcieClkSrcUsage[9]" = "5"             # PHY 4
  39         register "PcieClkSrcUsage[10]" = "6"            # PHY 2
  40         register "PcieClkSrcUsage[11]" = "7"            # PHY 1
  41         register "PcieClkSrcUsage[12]" = "13"           # PHY 0
  42         register "PcieClkSrcUsage[13]" = "0x42"         # PB
  43         register "PcieClkSrcUsage[14]" = "PCIE_CLK_NOTUSED"
  44         register "PcieClkSrcUsage[15]" = "PCIE_CLK_NOTUSED"
  45
  46         # Only enable CLKREQ# for M.2 slots
  47         register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
  48         register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
  49         register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
  50         register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
  51         register "PcieClkSrcClkReq[4]" = "4"                    # M2_M_CLK_REQ_n
  52         register "PcieClkSrcClkReq[5]" = "5"                    # M2_E_CLK_REQ_n
  53         register "PcieClkSrcClkReq[6]" = "PCIE_CLK_NOTUSED"
  54         register "PcieClkSrcClkReq[7]" = "PCIE_CLK_NOTUSED"
  55         register "PcieClkSrcClkReq[8]" = "PCIE_CLK_NOTUSED"
  56         register "PcieClkSrcClkReq[9]" = "PCIE_CLK_NOTUSED"
  57         register "PcieClkSrcClkReq[10]" = "PCIE_CLK_NOTUSED"
  58         register "PcieClkSrcClkReq[11]" = "PCIE_CLK_NOTUSED"
  59         register "PcieClkSrcClkReq[12]" = "PCIE_CLK_NOTUSED"
  60         register "PcieClkSrcClkReq[13]" = "PCIE_CLK_NOTUSED"
  61
  62         # USB OC5-7: not connected
  63         register "usb2_ports" = "{
  64
  65 #define HERMES_USB2_CONFIG(pin) { \
  66         .enable        = 1, \
  67         .ocpin         = (pin), \
  68         .tx_bias       = USB2_BIAS_0MV, \
  69         .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
  70         .pre_emp_bias  = USB2_BIAS_28P15MV, \
  71         .pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
  72 }
  73                 [0] = HERMES_USB2_CONFIG(OC0),          /* USB3 rear panel 1 */
  74                 [1] = HERMES_USB2_CONFIG(OC0),
  75                 [2] = HERMES_USB2_CONFIG(OC1),          /* USB3 rear panel 2 */
  76                 [3] = HERMES_USB2_CONFIG(OC1),
  77                 [4] = HERMES_USB2_CONFIG(OC2),          /* USB3 internal header CN_USB3_HDR */
  78                 [5] = HERMES_USB2_CONFIG(OC2),
  79                 [6] = HERMES_USB2_CONFIG(OC3),          /* USB2 internal header USB2_HDR1 */
  80                 [7] = HERMES_USB2_CONFIG(OC3),
  81                 [8] = HERMES_USB2_CONFIG(OC4),          /* USB2 internal header USB2_HDR1 */
  82                 [9] = HERMES_USB2_CONFIG(OC4),
  83                 [10] = HERMES_USB2_CONFIG(OC_SKIP),     /* BMC */
  84                 [11] = USB2_PORT_EMPTY,
  85                 [12] = HERMES_USB2_CONFIG(OC_SKIP),     /* piggy-back */
  86                 [13] = HERMES_USB2_CONFIG(OC_SKIP),     /* M.2 key E */
  87         }"
  88
  89         # USB Config 2.0/3.0
  90         # Enumeration starts at 0
  91         # USB 3.0
  92         # USB OC0: RP1
  93         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
  94         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
  95
  96         # USB OC1: RP2
  97         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
  98         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
  99
 100         # USB OC2:  Internal Header CN_USB3_HDR
 101         register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"
 102         register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)"
 103
 104         # Thermal
 105         register "tcc_offset" = "1"     # TCC of 99C
 106
 107         # Disable S0ix
 108         register "s0ix_enable" = "0"
 109
 110         # Enable Turbo
 111         register "eist_enable" = "1"
 112
 113         register "common_soc_config" = "{
 114                 .gspi[0] = {
 115                         .speed_mhz = 1,
 116                         .early_init = 1,
 117                 },
 118         }"
 119
 120         # VR Power Delivery Design
 121         register "VrPowerDeliveryDesign" = "0x12"
 122
 123         register "SerialIoDevMode" = "{
 124                 [PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
 125                 [PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
 126                 [PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
 127                 [PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
 128                 [PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
 129                 [PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
 130                 [PchSerialIoIndexSPI0]  = PchSerialIoPci,
 131                 [PchSerialIoIndexSPI1]  = PchSerialIoDisabled,
 132                 [PchSerialIoIndexUART0] = PchSerialIoPci,
 133                 [PchSerialIoIndexUART1] = PchSerialIoPci,
 134                 [PchSerialIoIndexUART2] = PchSerialIoPci,
 135         }"
 136
 137         register "DisableHeciRetry" = "1"
 138
 139         device domain 0 on
 140                 device ref system_agent on  end
 141                 device ref peg0 on # x8             / Slot 2
 142                         smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT2" "SlotDataBusWidth8X"
 143                 end
 144                 device ref peg1 on # x4 or x8       / Slot 6
 145                         smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT6" "SlotDataBusWidth4X"
 146                 end
 147                 device ref peg2 on # x4 or disabled / Slot 4
 148                         smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT4" "SlotDataBusWidth4X"
 149                 end
 150                 device ref igpu on end
 151                 device ref dptf on  end
 152                 device ref gna on  end
 153                 device ref thermal on  end
 154                 device ref xhci on  end
 155                 device ref xdci off end
 156                 device ref shared_sram on  end
 157                 device ref cnvi_wifi on
 158                         chip drivers/wifi/generic
 159                                 register "wake" = "PME_B0_EN_BIT"
 160                                 device generic 0 on end
 161                         end
 162                 end
 163                 device ref sdxc off end
 164                 device ref heci1 on  end
 165                 device ref heci2 on  end
 166                 device ref heci3 off end
 167                 device ref sata on  end
 168                 # This device does not have any function on CNP-H, but it needs
 169                 # to be here so that the resource allocator is aware of UART 2.
 170                 device ref i2c4 hidden end
 171                 device ref uart2 hidden end # in ACPI mode
 172                 device ref pcie_rp21 on
 173                         smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
 174                         register "PcieRpEnable[20]" = "1"
 175                         register "PcieRpLtrEnable[20]" = "1"
 176                         register "PcieRpSlotImplemented[20]" = "1"
 177                         register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
 178                         register "PcieRpAdvancedErrorReporting[20]" = "1"
 179                         register "PcieRpAspm[20]" = "AspmDisabled"
 180                 end
 181                 device ref pcie_rp1 on
 182                         smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
 183                         register "PcieRpEnable[0]" = "1"
 184                         register "PcieRpLtrEnable[0]" = "1"
 185                         register "PcieRpSlotImplemented[0]" = "1"
 186                         register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
 187                         register "PcieRpAdvancedErrorReporting[0]" = "1"
 188                         register "PcieRpAspm[0]" = "AspmDisabled"
 189                 end
 190                 device ref pcie_rp5 on  # PHY 3
 191                         register "PcieRpEnable[4]" = "1"
 192                         register "PcieRpLtrEnable[4]" = "1"
 193                         device pci 00.0 on
 194                                 smbios_dev_info 3
 195                         end
 196                 end
 197                 device ref pcie_rp6 on  # PHY 4
 198                         register "PcieRpEnable[5]" = "1"
 199                         register "PcieRpLtrEnable[5]" = "1"
 200                         device pci 00.0 on
 201                                 smbios_dev_info 4
 202                         end
 203                 end
 204                 device ref pcie_rp7 on  # PHY 2
 205                         register "PcieRpEnable[6]" = "1"
 206                         register "PcieRpLtrEnable[6]" = "1"
 207                         device pci 00.0 on
 208                                 smbios_dev_info 2
 209                         end
 210                 end
 211                 device ref pcie_rp8 on  # PHY 1
 212                         register "PcieRpEnable[7]" = "1"
 213                         register "PcieRpLtrEnable[7]" = "1"
 214                         device pci 00.0 on
 215                                 smbios_dev_info 1
 216                         end
 217                 end
 218                 device ref pcie_rp9 on
 219                         smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
 220                         register "PcieRpEnable[8]" = "1"
 221                         register "PcieRpLtrEnable[8]" = "1"
 222                         register "PcieRpSlotImplemented[8]" = "1"
 223                 end
 224                 device ref pcie_rp14 on # PHY 0
 225                         register "PcieRpEnable[13]" = "1"
 226                         register "PcieRpLtrEnable[13]" = "1"
 227                         device pci 00.0 on
 228                                 smbios_dev_info 0
 229                         end
 230                 end
 231                 device ref pcie_rp15 on # BMC
 232                         device pci 00.0 on      # Aspeed PCI Bridge
 233                                 device pci 00.0 on end  # Aspeed 2500 VGA
 234                         end
 235                         register "PcieRpEnable[14]" = "1"
 236                         register "PcieRpLtrEnable[14]" = "1"
 237                         register "PcieRpSlotImplemented[14]" = "1"
 238                 end
 239                 device ref pcie_rp16 on # M.2 E/CNVi
 240                         # Disabled when CNVi is present
 241                         register "PcieRpEnable[15]" = "1"
 242                         register "PcieRpLtrEnable[15]" = "1"
 243                         register "PcieRpSlotImplemented[15]" = "1"
 244                 end
 245                 device ref uart0 on  end
 246                 device ref uart1 on  end
 247                 device ref gspi0 off end
 248                 device ref gspi1 off end
 249                 device ref lpc_espi on
 250                         chip drivers/pc80/tpm
 251                                 device pnp 0c31.0 on end
 252                         end
 253                         # AST2500, but not enabled to decode LPC cycles
 254                 end
 255                 device ref p2sb on     end
 256                 device ref pmc hidden end
 257                 device ref hda on     end
 258                 device ref smbus on     end
 259                 device ref fast_spi on     end
 260         end
 261 end