src/mainboard/amd/gardenia/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <amdblocks/agesawrapper.h>
   5 #include <amdblocks/amd_pci_util.h>
   6 #include <soc/gpio.h>
   7 #include <soc/southbridge.h>
   8
   9 #include "gpio.h"
  10
  11 /***********************************************************
  12  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  13  * This table is responsible for physically routing the PIC and
  14  * IOAPIC IRQs to the different PCI devices on the system.  It
  15  * is read and written via registers 0xC00/0xC01 as an
  16  * Index/Data pair.  These values are chipset and mainboard
  17  * dependent and should be updated accordingly.
  18  *
  19  * These values are used by the PCI configuration space,
  20  * MP Tables.  TODO: Make ACPI use these values too.
  21  */
  22 static const u8 mainboard_picr_data[] = {
  23         [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F,
  24         [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
  25         [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F,
  26         [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  27         [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
  28         [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  29         [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05,
  30         [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  31         [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  32         [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  33         [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,
  34         [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
  35         [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
  36         [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
  37         [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
  38         [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
  39 };
  40
  41 static const u8 mainboard_intr_data[] = {
  42         [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
  43         [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
  44         [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10,
  45         [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00,
  46         [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
  47         [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  48         [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
  49         [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  50         [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  51         [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  52         [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
  53         [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  54         [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
  55         [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  56         [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
  57         [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  58 };
  59
  60 /* PIRQ Setup */
  61 static void pirq_setup(void)
  62 {
  63         intr_data_ptr = mainboard_intr_data;
  64         picr_data_ptr = mainboard_picr_data;
  65 }
  66
  67 static void mainboard_init(void *chip_info)
  68 {
  69         size_t num_gpios;
  70         const struct soc_amd_gpio *gpios;
  71         gpios = gpio_table(&num_gpios);
  72         gpio_configure_pads(gpios, num_gpios);
  73 }
  74
  75 /*************************************************
  76  * enable the dedicated function in gardenia board.
  77  *************************************************/
  78 static void mainboard_enable(struct device *dev)
  79 {
  80         /* Initialize the PIRQ data structures for consumption */
  81         pirq_setup();
  82 }
  83
  84 struct chip_operations mainboard_ops = {
  85         .init = mainboard_init,
  86         .enable_dev = mainboard_enable,
  87 };