src/mainboard/amd/mandolin/variants/cereme/devicetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/amd/picasso
   4         # ACP Configuration
   5         register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_MAX_HDA"
   6
   7         # Set FADT Configuration
   8         register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
   9         register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec
  10
  11         register "emmc_config" = "{
  12                 .timing = SD_EMMC_DISABLE,
  13         }"
  14
  15         register "has_usb2_phy_tune_params" = "1"
  16
  17         # Controller0 Port0 Default
  18         register "usb_2_port_tune_params[0]" = "{
  19                 .com_pds_tune = 0x03,
  20                 .sq_rx_tune = 0x3,
  21                 .tx_fsls_tune = 0x3,
  22                 .tx_pre_emp_amp_tune = 0x03,
  23                 .tx_pre_emp_pulse_tune = 0x0,
  24                 .tx_rise_tune = 0x1,
  25                 .tx_vref_tune = 0x6,
  26                 .tx_hsxv_tune = 0x3,
  27                 .tx_res_tune = 0x01,
  28         }"
  29
  30         # Controller0 Port1 Default
  31         register "usb_2_port_tune_params[1]" = "{
  32                 .com_pds_tune = 0x03,
  33                 .sq_rx_tune = 0x3,
  34                 .tx_fsls_tune = 0x3,
  35                 .tx_pre_emp_amp_tune = 0x03,
  36                 .tx_pre_emp_pulse_tune = 0x0,
  37                 .tx_rise_tune = 0x1,
  38                 .tx_vref_tune = 0x6,
  39                 .tx_hsxv_tune = 0x3,
  40                 .tx_res_tune = 0x01,
  41         }"
  42
  43         # Controller0 Port2 Default
  44         register "usb_2_port_tune_params[2]" = "{
  45                 .com_pds_tune = 0x03,
  46                 .sq_rx_tune = 0x3,
  47                 .tx_fsls_tune = 0x3,
  48                 .tx_pre_emp_amp_tune = 0x03,
  49                 .tx_pre_emp_pulse_tune = 0x0,
  50                 .tx_rise_tune = 0x1,
  51                 .tx_vref_tune = 0x6,
  52                 .tx_hsxv_tune = 0x3,
  53                 .tx_res_tune = 0x01,
  54         }"
  55
  56         # Controller0 Port3 Default
  57         register "usb_2_port_tune_params[3]" = "{
  58                 .com_pds_tune = 0x03,
  59                 .sq_rx_tune = 0x3,
  60                 .tx_fsls_tune = 0x3,
  61                 .tx_pre_emp_amp_tune = 0x03,
  62                 .tx_pre_emp_pulse_tune = 0x0,
  63                 .tx_rise_tune = 0x1,
  64                 .tx_vref_tune = 0x6,
  65                 .tx_hsxv_tune = 0x3,
  66                 .tx_res_tune = 0x01,
  67         }"
  68
  69         # Controller0 Port4 Default
  70         register "usb_2_port_tune_params[4]" = "{
  71                 .com_pds_tune = 0x03,
  72                 .sq_rx_tune = 0x3,
  73                 .tx_fsls_tune = 0x3,
  74                 .tx_pre_emp_amp_tune = 0x02,
  75                 .tx_pre_emp_pulse_tune = 0x0,
  76                 .tx_rise_tune = 0x1,
  77                 .tx_vref_tune = 0x5,
  78                 .tx_hsxv_tune = 0x3,
  79                 .tx_res_tune = 0x01,
  80         }"
  81
  82         # Controller0 Port5 Default
  83         register "usb_2_port_tune_params[5]" = "{
  84                 .com_pds_tune = 0x03,
  85                 .sq_rx_tune = 0x3,
  86                 .tx_fsls_tune = 0x3,
  87                 .tx_pre_emp_amp_tune = 0x02,
  88                 .tx_pre_emp_pulse_tune = 0x0,
  89                 .tx_rise_tune = 0x1,
  90                 .tx_vref_tune = 0x5,
  91                 .tx_hsxv_tune = 0x3,
  92                 .tx_res_tune = 0x01,
  93         }"
  94
  95         # USB OC pin mapping; all ports share one OC pin
  96         register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0"
  97         register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0"
  98         register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0"
  99         register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_0"
 100         register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0"
 101         register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0"
 102
 103         # eSPI Configuration
 104         register "common_config.espi_config" = "{
 105                 .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN,
 106                 .generic_io_range[0] = {
 107                         .base = 0x662,
 108                         .size = 8,
 109                 },
 110
 111                 .io_mode = ESPI_IO_MODE_SINGLE,
 112                 .op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
 113                 .crc_check_enable = 1,
 114                 .alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
 115                 .periph_ch_en = 0,
 116                 .vw_ch_en = 0,
 117                 .oob_ch_en = 0,
 118                 .flash_ch_en = 0,
 119         }"
 120
 121         # general purpose PCIe clock output configuration
 122         register "gpp_clk_config[0]" = "GPP_CLK_REQ"
 123         register "gpp_clk_config[1]" = "GPP_CLK_REQ"
 124         register "gpp_clk_config[2]" = "GPP_CLK_REQ"
 125         register "gpp_clk_config[3]" = "GPP_CLK_OFF"
 126         register "gpp_clk_config[4]" = "GPP_CLK_REQ"
 127         register "gpp_clk_config[5]" = "GPP_CLK_OFF"
 128         register "gpp_clk_config[6]" = "GPP_CLK_OFF"
 129
 130         register "pspp_policy" = "DXIO_PSPP_BALANCED"
 131
 132         device domain 0 on
 133                 subsystemid 0x1022 0x1510 inherit
 134                 device ref iommu on end
 135                 device ref gpp_bridge_0 on end # Bridge to PCIe Ethernet chip
 136                 device ref internal_bridge_a on
 137                         device ref gfx on  end # Internal GPU
 138                         device ref gfx_hda on end # Display HDA
 139                         device ref crypto on end # Crypto Coprocessor
 140                         device ref xhci_0 on end # USB 3.1
 141                         device ref xhci_1 off end # USB 3.1
 142                         device ref acp on end # Audio
 143                         device ref hda on end # HDA
 144                         device ref mp2 on  end # non-Sensor Fusion Hub device
 145                 end
 146                 device ref internal_bridge_b on
 147                         device ref sata off end # AHCI
 148                         device ref xgbe_0 off end # integrated Ethernet MAC
 149                         device ref xgbe_1 off end # integrated Ethernet MAC
 150                 end
 151                 device ref lpc_bridge on
 152                         # chip superio/smsc/sio1036 # optional debug card
 153                 end
 154         end # domain
 155
 156         device ref uart_0 on end # console
 157         device ref uart_1 on end
 158
 159 end     # chip soc/amd/picasso