src/mainboard/amd/mandolin/variants/mandolin/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <soc/gpio.h>
   4 #include "../../gpio.h"
   5
   6 /*
   7  * As a rule of thumb, GPIO pins used by coreboot should be initialized at
   8  * bootblock while GPIO pins used only by the OS should be initialized at
   9  * ramstage.
  10  */
  11 static const struct soc_amd_gpio gpio_set_stage_ram[] = {
  12         /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL, SCI */
  13         PAD_NF_SCI(GPIO_2, WAKE_L, PULL_UP, EDGE_LOW),
  14         /* SSD DEVSLP */
  15         PAD_NF(GPIO_5, DEVSLP0, PULL_NONE),
  16         /* Defeature SATA Express DEVSLP, as some boards are reworked
  17          * to tie this to GPIO23 to control power */
  18         PAD_GPI(GPIO_6, PULL_UP),
  19         /* I2S SDIN */
  20         PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
  21         /* I2S LRCLK */
  22         PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
  23         /* Blink */
  24         PAD_NF(GPIO_11, BLINK, PULL_NONE),
  25         /* APU_ALS_INT# */
  26         PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
  27         /* Finger print CS# */
  28         PAD_GPO(GPIO_31, HIGH),
  29         /* NFC IRQ */
  30         PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS),
  31         /* Rear camera power enable */
  32         PAD_GPO(GPIO_89, HIGH),
  33 };
  34
  35 void mainboard_program_gpios(void)
  36 {
  37         gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
  38 }