src/mainboard/amd/thatcher/OemCustomize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <AGESA.h>
   4 #include <PlatformMemoryConfiguration.h>
   5
   6 #include <northbridge/amd/agesa/state_machine.h>
   7
   8 /*
   9  * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
  10  *
  11  * Lane Id
  12  * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
  13  * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
  14  * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
  15  * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
  16  * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
  17  * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
  18  * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
  19  * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
  20  * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
  21  * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
  22  * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
  23  * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
  24  * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
  25  * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
  26  * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
  27  * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
  28  * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
  29  * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
  30  * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
  31  * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
  32  * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
  33  * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
  34  * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
  35  * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
  36  * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
  37  * 25 DP0_TX[P,N]1
  38  * 26 DP0_TX[P,N]2
  39  * 27 DP0_TX[P,N]3
  40  * 28 DP1_TX[P,N]0
  41  * 29 DP1_TX[P,N]1
  42  * 30 DP1_TX[P,N]2
  43  * 31 DP1_TX[P,N]3
  44  * 32 DP2_TX[P,N]0
  45  * 33 DP2_TX[P,N]1
  46  * 34 DP2_TX[P,N]2
  47  * 35 DP2_TX[P,N]3
  48  * 36 DP2_TX[P,N]4
  49  * 37 DP2_TX[P,N]5
  50  * 38 DP2_TX[P,N]6
  51  */
  52
  53 static const PCIe_PORT_DESCRIPTOR PortList[] = {
  54         /* PCIe port, Lanes 15:8, PCI Device Number 2, PCIE SLOT x8 */
  55         {
  56                 0,
  57                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 15, 8),
  58                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
  59                                 HotplugDisabled,
  60                                 PcieGenMaxSupported,
  61                                 PcieGenMaxSupported,
  62                                 AspmDisabled, 1)
  63         },
  64         /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
  65         {
  66                 0,
  67                 PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
  68                 PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3,
  69                                 HotplugDisabled,
  70                                 PcieGenMaxSupported,
  71                                 PcieGenMaxSupported,
  72                                 AspmDisabled, 1)
  73         },
  74
  75         /* PCIe port, Lanes 4, PCI Device Number 4, LAN */
  76         {
  77                 0,
  78                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
  79                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
  80                                 HotplugDisabled,
  81                                 PcieGenMaxSupported,
  82                                 PcieGenMaxSupported,
  83                                 AspmDisabled, 1)
  84         },
  85
  86         /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */
  87         {
  88                 0,
  89                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
  90                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
  91                                 HotplugDisabled,
  92                                 PcieGenMaxSupported,
  93                                 PcieGenMaxSupported,
  94                                 AspmDisabled, 1)
  95         },
  96
  97         /* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */
  98         {
  99                 0,
 100                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
 101                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
 102                                 HotplugDisabled,
 103                                 PcieGenMaxSupported,
 104                                 PcieGenMaxSupported,
 105                                 AspmDisabled, 1)
 106         },
 107
 108         /* PCIe port, Lanes 7, PCI Device Number 7, Disabled */
 109         {
 110                 0,
 111                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
 112                 PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
 113                                 HotplugDisabled,
 114                                 PcieGenMaxSupported,
 115                                 PcieGenMaxSupported,
 116                                 AspmDisabled, 1)
 117         },
 118
 119         /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
 120         {
 121                 DESCRIPTOR_TERMINATE_LIST,
 122                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
 123                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
 124                                 HotplugDisabled,
 125                                 PcieGenMaxSupported,
 126                                 PcieGenMaxSupported,
 127                                 AspmDisabled, 0)
 128         },
 129 };
 130
 131 static const PCIe_DDI_DESCRIPTOR DdiList[] = {
 132         // DP0 to HDMI0/DP0
 133         {
 134                 0,
 135                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
 136                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
 137         },
 138         // DP1 to HDMI1/DP1
 139         {
 140                 0,
 141                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
 142                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
 143         },
 144         // DP2 to MINI-DDI Card
 145         {
 146                 DESCRIPTOR_TERMINATE_LIST,
 147                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
 148                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
 149         },
 150 };
 151
 152 void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 153 {
 154         FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
 155         FchReset->Xhci0Enable = FALSE;
 156         FchReset->Xhci1Enable = FALSE;
 157 }
 158
 159 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 160         .Flags        = DESCRIPTOR_TERMINATE_LIST,
 161         .SocketId     = 0,
 162         .PciePortList = PortList,
 163         .DdiLinkList  = DdiList,
 164 };
 165
 166 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 167 {
 168         InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 169 }
 170
 171 /*----------------------------------------------------------------------------------------
 172  *                        CUSTOMER OVERRIDES MEMORY TABLE
 173  *----------------------------------------------------------------------------------------
 174  */
 175
 176 /*
 177  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
 178  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
 179  *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
 180  *  use its default conservative settings.
 181  */
 182 static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
 183   NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
 184   NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
 185   MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
 186   CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
 187   ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
 188   CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
 189
 190   PSO_END
 191 };
 192
 193 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 194 {
 195         InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
 196 }
 197
 198 void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
 199 {
 200         /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
 201         InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
 202 }