src/mainboard/aopen/dxplplusu/acpi_tables.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * Ported to Intel XE7501DEVKIT by Agami Aruma
   5  * Ported to AOpen DXPL Plus-U by Kyösti Mälkki
   6  */
   7
   8 #include <acpi/acpi.h>
   9 #include <device/pci_def.h>
  10
  11 #define IOAPIC_ICH4             2
  12 #define IOAPIC_P64H2_BUS_B      3       /* IOAPIC 3 at 02:1c.0 */
  13 #define IOAPIC_P64H2_BUS_A      4       /* IOAPIC 4 at 02:1e.0 */
  14
  15 #define INTEL_IOAPIC_NUM_INTERRUPTS     24      /* Both ICH-4 and P64-H2 */
  16
  17 unsigned long acpi_fill_madt(unsigned long current)
  18 {
  19         unsigned int irq_start = 0;
  20         struct device *bdev, *dev = NULL;
  21         struct resource* res = NULL;
  22
  23         /* SJM: Hard-code CPU LAPIC entries for now */
  24         current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
  25         current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6);
  26         current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1);
  27         current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7);
  28
  29         /* Southbridge IOAPIC */
  30         current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4,
  31                                            0xfec00000, irq_start);
  32         irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
  33
  34         bdev = pcidev_on_root(2, 0);
  35         /* P64H2 Bus B IOAPIC */
  36         if (bdev)
  37                 dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(28, 0));
  38         if (dev) {
  39                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
  40                 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
  41                                                    IOAPIC_P64H2_BUS_B, res->base, irq_start);
  42                 irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
  43         }
  44
  45         /* P64H2 Bus A IOAPIC */
  46         if (bdev)
  47                 dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(30, 0));
  48         if (dev) {
  49                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
  50                 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
  51                                                    IOAPIC_P64H2_BUS_A, res->base, irq_start);
  52                 irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
  53         }
  54
  55         /* Map ISA IRQ 0 to IRQ 2 */
  56         current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
  57
  58         /* IRQ9 differs from ISA standard - ours is active high, level-triggered */
  59         current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
  60
  61         return current;
  62 }