src/mainboard/asrock/b75pro3-m/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <device/pnp_ops.h>
   5 #include <northbridge/intel/sandybridge/raminit_native.h>
   6 #include <southbridge/intel/bd82x6x/pch.h>
   7 #include <superio/nuvoton/nct6776/nct6776.h>
   8 #include <superio/nuvoton/common/nuvoton.h>
   9
  10 #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
  11
  12 const struct southbridge_usb_port mainboard_usb_ports[] = {
  13         { 1, 0, 0 },
  14         { 1, 0, 0 },
  15         { 1, 1, 1 },
  16         { 1, 1, 1 },
  17         { 1, 1, 2 },
  18         { 1, 1, 2 },
  19         { 1, 0, 3 },
  20         { 1, 0, 3 },
  21         { 1, 0, 4 },
  22         { 1, 0, 4 },
  23         { 1, 0, 6 },
  24         { 1, 1, 5 },
  25         { 1, 1, 5 },
  26         { 1, 0, 6 },
  27 };
  28
  29 void bootblock_mainboard_early_init(void)
  30 {
  31         /* Set GPIOs on superio, enable UART */
  32         nuvoton_pnp_enter_conf_state(SERIAL_DEV);
  33         pnp_set_logical_device(SERIAL_DEV);
  34
  35         pnp_write_config(SERIAL_DEV, 0x1c, 0x80);
  36         pnp_write_config(SERIAL_DEV, 0x27, 0x80);
  37         pnp_write_config(SERIAL_DEV, 0x2a, 0x60);
  38
  39         nuvoton_pnp_exit_conf_state(SERIAL_DEV);
  40
  41         nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  42 }
  43
  44 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
  45 {
  46         read_spd(&spd[0], 0x50, id_only);
  47         read_spd(&spd[1], 0x51, id_only);
  48         read_spd(&spd[2], 0x52, id_only);
  49         read_spd(&spd[3], 0x53, id_only);
  50 }