src/mainboard/asrock/e350m1/OemCustomize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <AGESA.h>
   4 #include <PlatformMemoryConfiguration.h>
   5
   6 #include <northbridge/amd/agesa/state_machine.h>
   7
   8 static const PCIe_PORT_DESCRIPTOR PortList[] = {
   9         // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
  10         {
  11                 0,
  12                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
  13                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
  14                                 HotplugDisabled,
  15                                 PcieGen2,
  16                                 PcieGen2,
  17                                 AspmL0sL1, 0)
  18         },
  19         // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
  20         {
  21                 DESCRIPTOR_TERMINATE_LIST,
  22                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
  23                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
  24                                 HotplugDisabled,
  25                                 PcieGen2,
  26                                 PcieGen2,
  27                                 AspmL0sL1, 0)
  28         }
  29 };
  30
  31 static const PCIe_DDI_DESCRIPTOR DdiList[] = {
  32         // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
  33         {
  34                 0,
  35                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
  36                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
  37         },
  38         // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
  39         {
  40                 DESCRIPTOR_TERMINATE_LIST,
  41                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
  42                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
  43         }
  44 };
  45
  46 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
  47         .Flags        = DESCRIPTOR_TERMINATE_LIST,
  48         .SocketId     = 0,
  49         .PciePortList = PortList,
  50         .DdiLinkList  = DdiList,
  51 };
  52
  53 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
  54 {
  55         InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
  56         InitEarly->GnbConfig.PsppPolicy         = 0;
  57 }
  58
  59 /*----------------------------------------------------------------------------------------
  60  *                        CUSTOMER OVERRIDES MEMORY TABLE
  61  *----------------------------------------------------------------------------------------
  62  */
  63
  64 /*
  65  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
  66  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
  67  *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
  68  *  use its default conservative settings.
  69  */
  70 static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
  71   NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
  72   NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
  73   PSO_END
  74 };
  75
  76 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
  77 {
  78         InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
  79 }