src/mainboard/asrock/e350m1/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/acpimmio.h>
   4 #include <device/device.h>
   5 #include <southbridge/amd/common/amd_pci_util.h>
   6 #include <device/mmio.h>
   7 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
   8
   9 static const u8 mainboard_intr_data[] = {
  10         [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,  /* INTA# - INTH# */
  11         [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
  12         [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  13         0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  14         0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  15         0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  16         0x10, 0x11, 0x12, 0x13
  17 };
  18
  19 /* PIRQ Setup */
  20 static void pirq_setup(void)
  21 {
  22         intr_data_ptr = mainboard_intr_data;
  23 }
  24
  25 /**********************************************
  26  * Enable the dedicated functions of the board.
  27  **********************************************/
  28 static void mainboard_enable(struct device *dev)
  29 {
  30         pirq_setup();
  31
  32         /* Power off unused clock pins of GPP PCIe devices
  33          * GPP CLK0 connected to unpopulated mini PCIe slot
  34          * GPP CLK1 connected to ethernet chip
  35          */
  36         misc_write8(0, 0xff);
  37         /* GPP CLK2 connected to the external USB3 controller */
  38         misc_write8(1, 0x0f);
  39         misc_write8(2, 0);
  40         misc_write8(3, 0);
  41         /* SLT_GFX_CLK connected to PCIe slot */
  42         misc_write8(4, 0xf0);
  43
  44         /*
  45          * Initialize ASF registers to an arbitrary address because someone
  46          * long ago set things up this way inside the SPD read code.  The
  47          * SPD read code has been made generic and moved out of the board
  48          * directory, so the ASF init is being done here.
  49          */
  50         pm_write8(0x29, 0x80);
  51         pm_write8(0x28, 0x61);
  52 }
  53
  54 struct chip_operations mainboard_ops = {
  55         .enable_dev = mainboard_enable,
  56 };