src/mainboard/asrock/e350m1/platform_cfg.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _PLATFORM_CFG_H_
   4 #define _PLATFORM_CFG_H_
   5
   6 /**
   7  * @def BIOS_SIZE
   8  *      BIOS_SIZE_{1,2,4,8,16}M
   9  *
  10  * In SB800, default ROM size is 1M Bytes, if your platform ROM
  11  * bigger than 1M you have to set the ROM size outside CIMx module and
  12  * before AGESA module get call.
  13  */
  14 #ifndef BIOS_SIZE
  15 #define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
  16 #endif /* BIOS_SIZE */
  17
  18 /**
  19  * @def SPREAD_SPECTRUM
  20  * @brief
  21  *  0 - Disable Spread Spectrum function
  22  *  1 - Enable  Spread Spectrum function
  23  */
  24 #define SPREAD_SPECTRUM                 0
  25
  26 /**
  27  * @def SB_HPET_TIMER
  28  * @brief
  29  *  0 - Disable hpet
  30  *  1 - Enable  hpet
  31  */
  32 #define HPET_TIMER                      1
  33
  34 /**
  35  * @def USB_CONFIG
  36  * @brief bit[0-6] used to control USB
  37  *   0 - Disable
  38  *   1 - Enable
  39  *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
  40  *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
  41  *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
  42  *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
  43  *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
  44  *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
  45  *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
  46  */
  47 #define USB_CONFIG              0x7F
  48
  49 /**
  50  * @def PCI_CLOCK_CTRL
  51  * @brief bit[0-4] used for PCI Slots Clock Control,
  52  *   0 - disable
  53  *   1 - enable
  54  *  PCI SLOT 0 define at BIT0
  55  *  PCI SLOT 1 define at BIT1
  56  *  PCI SLOT 2 define at BIT2
  57  *  PCI SLOT 3 define at BIT3
  58  *  PCI SLOT 4 define at BIT4
  59  */
  60 #define PCI_CLOCK_CTRL                  0x1F
  61
  62 /**
  63  * @def SATA_CONTROLLER
  64  * @brief INCHIP Sata Controller
  65  */
  66 #define SATA_CONTROLLER         CIMX_OPTION_ENABLED
  67
  68 /**
  69  * @def SATA_MODE
  70  * @brief INCHIP Sata Controller Mode
  71  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  72  */
  73 #define SATA_MODE                       CONFIG_SB800_SATA_MODE
  74
  75 /**
  76  * @brief INCHIP Sata IDE Controller Mode
  77  */
  78 #define IDE_LEGACY_MODE                 0
  79 #define IDE_NATIVE_MODE                 1
  80
  81 /**
  82  * @def SATA_IDE_MODE
  83  * @brief INCHIP Sata IDE Controller Mode
  84  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  85  */
  86 #define SATA_IDE_MODE                   IDE_LEGACY_MODE
  87
  88 /**
  89  * @def EXTERNAL_CLOCK
  90  * @brief 00/10: Reference clock from crystal oscillator via
  91  *  PAD_XTALI and PAD_XTALO
  92  *
  93  * @def INTERNAL_CLOCK
  94  * @brief 01/11: Reference clock from internal clock through
  95  *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
  96  */
  97 #define EXTERNAL_CLOCK          0x00
  98 #define INTERNAL_CLOCK          0x01
  99
 100 /* NOTE: inagua have to using internal clock,
 101  * otherwise can not detect sata drive
 102  */
 103 #define SATA_CLOCK_SOURCE       INTERNAL_CLOCK
 104
 105 /**
 106  * @def SATA_PORT_MULT_CAP_RESERVED
 107  * @brief 1 ON, 0 0FF
 108  */
 109 #define SATA_PORT_MULT_CAP_RESERVED     1
 110
 111 /**
 112  * @def   AZALIA_AUTO
 113  * @brief Detect Azalia controller automatically.
 114  *
 115  * @def   AZALIA_DISABLE
 116  * @brief Disable Azalia controller.
 117
 118  * @def   AZALIA_ENABLE
 119  * @brief Enable Azalia controller.
 120  */
 121 #define AZALIA_AUTO                     0
 122 #define AZALIA_DISABLE                  1
 123 #define AZALIA_ENABLE                   2
 124
 125 /**
 126  * @brief INCHIP HDA controller
 127  */
 128 #define AZALIA_CONTROLLER               AZALIA_AUTO
 129
 130 /**
 131  * @def AZALIA_PIN_CONFIG
 132  * @brief
 133  *  0 - disable
 134  *  1 - enable
 135  */
 136 #define AZALIA_PIN_CONFIG               1
 137
 138 /**
 139  * @def AZALIA_SDIN_PIN
 140  * @brief
 141  *  SDIN0 is defined at BIT0 & BIT1
 142  *   00 - GPIO PIN
 143  *   01 - Reserved
 144  *   10 - As a Azalia SDIN pin
 145  *  SDIN1 is defined at BIT2 & BIT3
 146  *  SDIN2 is defined at BIT4 & BIT5
 147  *  SDIN3 is defined at BIT6 & BIT7
 148  */
 149 //#define AZALIA_SDIN_PIN               0xAA
 150 #define AZALIA_SDIN_PIN                 0x2A
 151
 152 /**
 153  * @def GPP_CONTROLLER
 154  */
 155 #define GPP_CONTROLLER                  CIMX_OPTION_ENABLED
 156
 157 /**
 158  * @def GPP_CFGMODE
 159  * @brief GPP Link Configuration
 160  * four possible configuration:
 161  *  GPP_CFGMODE_X4000
 162  *  GPP_CFGMODE_X2200
 163  *  GPP_CFGMODE_X2110
 164  *  GPP_CFGMODE_X1111
 165  */
 166 #define GPP_CFGMODE                     GPP_CFGMODE_X1111
 167
 168 /**
 169  * @def NB_SB_GEN2
 170  *    0  - Disable
 171  *    1  - Enable
 172  */
 173 #define NB_SB_GEN2                      TRUE
 174
 175 /**
 176  * @def SB_GPP_GEN2
 177  *    0  - Disable
 178  *    1  - Enable
 179  */
 180 #define SB_GPP_GEN2                     TRUE
 181
 182 /**
 183  * @def SB_GPP_UNHIDE_PORTS
 184  *    TRUE   - ports visible always, even port empty
 185  *    FALSE  - ports invisible if port empty
 186  */
 187 #define SB_GPP_UNHIDE_PORTS             FALSE
 188
 189 /**
 190  * @def   GEC_CONFIG
 191  *    0  - Enable
 192  *    1  - Disable
 193  */
 194 #define GEC_CONFIG                      0
 195
 196 /**
 197  * @def SIO_HWM_BASE_ADDRESS
 198  *    Super IO HWM base address
 199  */
 200 #define SIO_HWM_BASE_ADDRESS            0x290
 201
 202 #endif