src/mainboard/asrock/g41c-gs/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <bootblock_common.h>
   4 #include <device/pnp_ops.h>
   5 #include <northbridge/intel/x4x/x4x.h>
   6 #include <southbridge/intel/i82801gx/i82801gx.h>
   7 #include <superio/nuvoton/common/nuvoton.h>
   8 #include <superio/nuvoton/nct6776/nct6776.h>
   9 #include <superio/winbond/common/winbond.h>
  10 #include <superio/winbond/w83627dhg/w83627dhg.h>
  11
  12 #define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1)
  13 #define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)
  14
  15 void bootblock_mainboard_early_init(void)
  16 {
  17         /* Set GPIOs on superio, enable UART */
  18         if (CONFIG(SUPERIO_NUVOTON_NCT6776)) {
  19                 nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2);
  20                 pnp_set_logical_device(SERIAL_DEV_R2);
  21
  22                 pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80);
  23                 pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80);
  24                 pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60);
  25
  26                 nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2);
  27                 nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE);
  28         } else {
  29                 winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE);
  30         }
  31         /* IRQ routing */
  32         RCBA16(D31IR) = 0x0132;
  33         RCBA16(D29IR) = 0x0237;
  34 }
  35
  36 void mb_get_spd_map(u8 spd_map[4])
  37 {
  38         spd_map[0] = 0x50;
  39         spd_map[2] = 0x52;
  40 }