src/mainboard/asrock/imb-a180/OemCustomize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <AGESA.h>
   4 #include <PlatformMemoryConfiguration.h>
   5
   6 #include <northbridge/amd/agesa/state_machine.h>
   7
   8 static const PCIe_PORT_DESCRIPTOR PortList[] = {
   9         {
  10                 0,
  11                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
  12                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
  13                                 HotplugDisabled,
  14                                 PcieGenMaxSupported,
  15                                 PcieGenMaxSupported,
  16                                 AspmDisabled, 0x01, 0)
  17         },
  18         /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
  19         {
  20                 0,
  21                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
  22                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
  23                                 HotplugDisabled,
  24                                 PcieGenMaxSupported,
  25                                 PcieGenMaxSupported,
  26                                 AspmDisabled, 0x02, 0)
  27         },
  28         /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
  29         {
  30                 0,
  31                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
  32                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
  33                                 HotplugDisabled,
  34                                 PcieGenMaxSupported,
  35                                 PcieGenMaxSupported,
  36                                 AspmDisabled, 0x03, 0)
  37         },
  38         /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
  39         {
  40                 0,
  41                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
  42                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
  43                                 HotplugDisabled,
  44                                 PcieGenMaxSupported,
  45                                 PcieGenMaxSupported,
  46                                 AspmDisabled, 0x04, 0)
  47         },
  48         /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
  49         {
  50                 DESCRIPTOR_TERMINATE_LIST,
  51                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
  52                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
  53                                 HotplugDisabled,
  54                                 PcieGenMaxSupported,
  55                                 PcieGenMaxSupported,
  56                                 AspmDisabled, 0x05, 0)
  57         }
  58 };
  59
  60 static const PCIe_DDI_DESCRIPTOR DdiList[] = {
  61         /* DP0 to HDMI0/DP */
  62         {
  63                 0,
  64                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
  65                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
  66         },
  67         /* DP1 to FCH */
  68         {
  69                 0,
  70                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
  71                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
  72         },
  73         /* DP2 to HDMI1/DP */
  74         {
  75                 DESCRIPTOR_TERMINATE_LIST,
  76                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
  77                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3)
  78         },
  79 };
  80
  81 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
  82         .Flags        = DESCRIPTOR_TERMINATE_LIST,
  83         .SocketId     = 0,
  84         .PciePortList = PortList,
  85         .DdiLinkList  = DdiList
  86 };
  87
  88 void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
  89 {
  90         FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
  91         FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
  92         FchReset->Xhci1Enable = FALSE;
  93 }
  94
  95 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
  96 {
  97         InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
  98 }
  99
 100 /*----------------------------------------------------------------------------------------
 101  *                        CUSTOMER OVERRIDES MEMORY TABLE
 102  *----------------------------------------------------------------------------------------
 103  */
 104
 105 /*
 106  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
 107  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
 108  *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
 109  *  use its default conservative settings.
 110  */
 111 static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
 112
 113         #define SEED_A 0x12
 114         HW_RXEN_SEED(
 115                 ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
 116                 SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
 117                 SEED_A),
 118
 119   NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
 120   NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
 121   MOTHER_BOARD_LAYERS(LAYERS_4),
 122
 123   MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
 124   CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
 125   ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
 126   CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
 127
 128   PSO_END
 129 };
 130
 131 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 132 {
 133         InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
 134 }
 135
 136 void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
 137 {
 138         /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
 139         InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
 140 }