src/mainboard/bap/ode_e20XX/OemCustomize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <AGESA.h>
   4 #include <PlatformMemoryConfiguration.h>
   5
   6 #include <northbridge/amd/agesa/state_machine.h>
   7
   8
   9 static const PCIe_PORT_DESCRIPTOR PortList[] = {
  10         /* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device Number 2, Function 4) */
  11         {
  12                 0,
  13                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 3),
  14                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
  15                                 HotplugBasic,
  16                                 PcieGenMaxSupported,
  17                                 PcieGenMaxSupported,
  18                                 AspmDisabled, 0x02, 0)
  19         },
  20         /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device Number 2, Function 3) */
  21         {
  22                 0,
  23                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
  24                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
  25                                 HotplugDisabled,
  26                                 PcieGenMaxSupported,
  27                                 PcieGenMaxSupported,
  28                                 AspmDisabled, 0x03, 0)
  29         },
  30         /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device Number 2, Function 2) */
  31         {
  32                 0,
  33                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
  34                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
  35                                 HotplugDisabled,
  36                                 PcieGenMaxSupported,
  37                                 PcieGenMaxSupported,
  38                                 AspmDisabled, 0x04, 0)
  39         },
  40         /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, Function 1) */
  41         {
  42                 DESCRIPTOR_TERMINATE_LIST,
  43                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
  44                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
  45                                 HotplugBasic,
  46                                 PcieGenMaxSupported,
  47                                 PcieGenMaxSupported,
  48                                 AspmDisabled, 0x05, 0)
  49         }
  50 };
  51
  52 static const PCIe_DDI_DESCRIPTOR DdiList[] = {
  53         /* eDP0 to LVDS connector*/
  54         {
  55                 0,
  56                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
  57                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
  58         },
  59         /* DP1 to HDMI */
  60         {
  61                 DESCRIPTOR_TERMINATE_LIST,
  62                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
  63                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
  64         },
  65 };
  66
  67 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
  68         .Flags        = DESCRIPTOR_TERMINATE_LIST,
  69         .SocketId     = 0,
  70         .PciePortList = PortList,
  71         .DdiLinkList  = DdiList
  72 };
  73
  74 void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
  75 {
  76         FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
  77         FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
  78         FchReset->Xhci1Enable = FALSE;
  79 }
  80
  81 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
  82 {
  83         InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
  84 }
  85
  86 /*----------------------------------------------------------------------------------------
  87  *                        CUSTOMER OVERRIDES MEMORY TABLE
  88  *----------------------------------------------------------------------------------------
  89  */
  90
  91 /*
  92  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
  93  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
  94  *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
  95  *  use its default conservative settings.
  96  */
  97 static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
  98
  99         #define SEED_WL 0x0E
 100         WRITE_LEVELING_SEED(
 101                 ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
 102                 SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
 103                 SEED_WL),
 104
 105         #define SEED_A 0x12
 106         HW_RXEN_SEED(
 107                 ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
 108                 SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
 109                 SEED_A),
 110
 111   NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
 112   NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
 113   MOTHER_BOARD_LAYERS(LAYERS_6),
 114
 115   MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
 116   CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
 117   ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
 118   CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
 119
 120   PSO_END
 121 };
 122
 123 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 124 {
 125         InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
 126 }
 127
 128 void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
 129 {
 130         /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
 131         InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
 132 }