payloads/edk2: Disable the CPU Timer Lib unless supported
[coreboot.git] / src / mainboard / compulab / intense_pc / early_init.c
blobd3842f83f5987dc23c7257fe35163e1919b08680
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <bootblock_common.h>
4 #include <stdint.h>
5 #include <arch/io.h>
6 #include <northbridge/intel/sandybridge/raminit_native.h>
7 #include <superio/smsc/sio1007/sio1007.h>
8 #include <southbridge/intel/bd82x6x/pch.h>
10 #define SIO_PORT 0x164e
12 const struct southbridge_usb_port mainboard_usb_ports[] = {
13 { 1, 1, 0 },
14 { 1, 1, 0 },
15 { 1, 1, 1 },
16 { 1, 1, 1 },
17 { 1, 0, 2 },
18 { 1, 0, 2 },
19 { 1, 0, 3 },
20 { 1, 0, 3 },
21 { 1, 1, 4 },
22 { 1, 1, 4 },
23 { 1, 0, 5 },
24 { 1, 0, 5 },
25 { 1, 0, 6 },
26 { 1, 0, 6 },
29 void bootblock_mainboard_early_init(void)
31 const u16 port = SIO_PORT;
32 const u16 runtime_port = 0x180;
34 /* Enable COM1 if requested */
35 if (CONFIG(DRIVERS_UART_8250IO))
36 sio1007_enable_uart_at(port);
38 /* Turn on configuration mode. */
39 outb(0x55, port);
41 /* Set the GPIO direction, polarity, and type. */
42 sio1007_setreg(port, 0x31, 1 << 0, 1 << 0);
43 sio1007_setreg(port, 0x32, 0 << 0, 1 << 0);
44 sio1007_setreg(port, 0x33, 0 << 0, 1 << 0);
46 /* Set the base address for the runtime register block. */
47 sio1007_setreg(port, 0x30, runtime_port >> 4, 0xff);
48 sio1007_setreg(port, 0x21, runtime_port >> 12, 0xff);
50 /* Turn on address decoding for it. */
51 sio1007_setreg(port, 0x3a, 1 << 1, 1 << 1);
53 /* Set the value of GPIO 10 by changing GP1, bit 0. */
54 u8 byte;
55 byte = inb(runtime_port + 0xc);
56 byte |= (1 << 0);
57 outb(byte, runtime_port + 0xc);
59 /* Turn off address decoding for it. */
60 sio1007_setreg(port, 0x3a, 0 << 1, 1 << 1);
62 /* Turn off configuration mode. */
63 outb(0xaa, port);
66 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
68 read_spd(&spd[0], 0x50, id_only);
69 read_spd(&spd[2], 0x52, id_only);