src/mainboard/emulation/qemu-q35/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/pci_ops.h>
   4 #include <bootblock_common.h>
   5 #include <southbridge/intel/common/early_spi.h>
   6 #include <southbridge/intel/i82801ix/i82801ix.h>
   7
   8 #include "q35.h"
   9
  10 static void bootblock_northbridge_init(void)
  11 {
  12         /*
  13          * The "io" variant of the config access is explicitly used to
  14          * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to
  15          * to true. That way all subsequent non-explicit config accesses use
  16          * MCFG. This code also assumes that bootblock_northbridge_init() is
  17          * the first thing called in the non-asm boot block code. The final
  18          * assumption is that no assembly code is using the
  19          * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
  20          *
  21          * The PCIEXBAR is assumed to live in the memory mapped IO space under
  22          * 4GiB.
  23          */
  24         const uint32_t pciexbar = make_pciexbar();
  25         pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_HI, 0);
  26         pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, pciexbar);
  27
  28         if (CONFIG(BOOTBLOCK_CONSOLE))
  29                 mainboard_machine_check();
  30 }
  31
  32 static void bootblock_southbridge_init(void)
  33 {
  34         enable_spi_prefetching_and_caching();
  35
  36         /* Enable RCBA */
  37         pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA,
  38                         CONFIG_FIXED_RCBA_MMIO_BASE | 1);
  39 }
  40
  41 void bootblock_soc_init(void)
  42 {
  43         bootblock_northbridge_init();
  44         bootblock_southbridge_init();
  45 }