src/mainboard/facebook/monolith/devicetree.cb

   1 chip soc/intel/skylake
   2
   3         register "deep_s5_enable_ac" = "0"
   4         register "deep_s5_enable_dc" = "0"
   5         register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
   6
   7         # GPE configuration
   8         # Note that GPE events called out in ASL code rely on this
   9         # route. i.e. If this route changes then the affected GPE
  10         # offset bits also need to be changed.
  11         register "gpe0_dw0" = "GPP_C"
  12         register "gpe0_dw1" = "GPP_D"
  13         register "gpe0_dw2" = "GPP_E"
  14
  15         # Set the fixed lpc ranges
  16         # enable COMA at 3f8 and COMB at 3e8 (instead of the default 2f8)
  17         # enable the embedded controller
  18         register "lpc_iod" = "0x0070"
  19         register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66"
  20
  21         # CPLD host command ranges are in 0x280-0x2BF
  22         # EC PNP registers are at 0x6e and 0x6f
  23         register "gen1_dec" = "0x003c0281"
  24         register "gen3_dec" = "0x0004006d"
  25
  26         # LPC serial IRQ
  27         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  28
  29         # "Intel SpeedStep Technology"
  30         register "eist_enable" = "1"
  31
  32         # DPTF
  33         register "dptf_enable" = "1"
  34
  35         # FSP Configuration
  36         register "ScsEmmcHs400Enabled" = "1"
  37         register "SkipExtGfxScan" = "1"
  38         register "SaGv" = "SaGv_Enabled"
  39
  40         register "SataSalpSupport" = "1"
  41         register "SataPortsEnable" = "{ \
  42                 [0]     = 1, \
  43                 [1]     = 0, \
  44                 [2]     = 0, \
  45                 [3]     = 0, \
  46                 [4]     = 0, \
  47                 [5]     = 0, \
  48                 [6]     = 0, \
  49                 [7]     = 0, \
  50         }"
  51
  52         # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
  53         # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
  54         register "PmConfigSlpS3MinAssert" = "2"
  55
  56         # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
  57         register "PmConfigSlpS4MinAssert" = "4"
  58
  59         # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
  60         register "PmConfigSlpSusMinAssert" = "3"
  61
  62         # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
  63         register "PmConfigSlpAMinAssert" = "3"
  64
  65         # VR Settings Configuration for 4 Domains
  66         #+----------------+-------+-------+-------+-------+
  67         #| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
  68         #+----------------+-------+-------+-------+-------+
  69         #| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
  70         #| Psi2Threshold  | 5A    | 5A    | 5A    | 5A    |
  71         #| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
  72         #| Psi3Enable     | 1     | 1     | 1     | 1     |
  73         #| Psi4Enable     | 1     | 1     | 1     | 1     |
  74         #| ImonSlope      | 0     | 0     | 0     | 0     |
  75         #| ImonOffset     | 0     | 0     | 0     | 0     |
  76         #| IccMax         | 5.1A  | 32A   | 35A   | 31A   |
  77         #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
  78         #+----------------+-------+-------+-------+-------+
  79         register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
  80                 .vr_config_enable = 1, \
  81                 .psi1threshold = VR_CFG_AMP(20), \
  82                 .psi2threshold = VR_CFG_AMP(5), \
  83                 .psi3threshold = VR_CFG_AMP(1), \
  84                 .psi3enable = 1, \
  85                 .psi4enable = 1, \
  86                 .imon_slope = 0, \
  87                 .imon_offset = 0, \
  88                 .icc_max = VR_CFG_AMP(5.1), \
  89                 .voltage_limit = 1520 \
  90         }"
  91
  92         register "domain_vr_config[VR_IA_CORE]" = "{
  93                 .vr_config_enable = 1, \
  94                 .psi1threshold = VR_CFG_AMP(20), \
  95                 .psi2threshold = VR_CFG_AMP(5), \
  96                 .psi3threshold = VR_CFG_AMP(1), \
  97                 .psi3enable = 1, \
  98                 .psi4enable = 1, \
  99                 .imon_slope = 0, \
 100                 .imon_offset = 0, \
 101                 .icc_max = VR_CFG_AMP(32), \
 102                 .voltage_limit = 1520 \
 103         }"
 104
 105         register "domain_vr_config[VR_GT_UNSLICED]" = "{
 106                 .vr_config_enable = 1, \
 107                 .psi1threshold = VR_CFG_AMP(20), \
 108                 .psi2threshold = VR_CFG_AMP(5), \
 109                 .psi3threshold = VR_CFG_AMP(1), \
 110                 .psi3enable = 1, \
 111                 .psi4enable = 1, \
 112                 .imon_slope = 0, \
 113                 .imon_offset = 0, \
 114                 .icc_max = VR_CFG_AMP(35),\
 115                 .voltage_limit = 1520 \
 116         }"
 117
 118         register "domain_vr_config[VR_GT_SLICED]" = "{
 119                 .vr_config_enable = 1, \
 120                 .psi1threshold = VR_CFG_AMP(20), \
 121                 .psi2threshold = VR_CFG_AMP(5), \
 122                 .psi3threshold = VR_CFG_AMP(1), \
 123                 .psi3enable = 1, \
 124                 .psi4enable = 1, \
 125                 .imon_slope = 0, \
 126                 .imon_offset = 0, \
 127                 .icc_max = VR_CFG_AMP(31), \
 128                 .voltage_limit = 1520 \
 129         }"
 130
 131         # Send an extra VR mailbox command for the PS4 exit issue
 132         register "SendVrMbxCmd" = "2"
 133
 134         # Enable Root ports.
 135         # PCIE Port 1 disabled
 136         # PCIE Port 2 disabled
 137
 138         # PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard
 139         register "PcieRpEnable[2]" = "1"
 140         # Disable CLKREQ#
 141         register "PcieRpClkReqSupport[2]" = "0"
 142         # Set MaxPayload to 256 bytes
 143         register "PcieRpMaxPayload[2]" = "RpMaxPayload_256"
 144         # Enable Latency Tolerance Reporting Mechanism
 145         register "PcieRpLtrEnable[2]" = "1"
 146         # Enable Advanced Error Reporting
 147         register "PcieRpAdvancedErrorReporting[2]" = "1"
 148         # Disable Aspm
 149         register "pcie_rp_aspm[2]" = "AspmDisabled"
 150
 151         # PCIE Port 4 disabled
 152         # PCIE Port 5 x1 -> MODULE i219
 153
 154         # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard
 155         register "PcieRpEnable[5]" = "1"
 156         register "PcieRpClkReqSupport[5]" = "0"
 157         # Set MaxPayload to 256 bytes
 158         register "PcieRpMaxPayload[5]" = "RpMaxPayload_256"
 159         # Enable Latency Tolerance Reporting Mechanism
 160         register "PcieRpLtrEnable[5]" = "1"
 161         # Enable Advanced Error Reporting
 162         register "PcieRpAdvancedErrorReporting[5]" = "1"
 163         # Disable Aspm
 164         register "pcie_rp_aspm[5]" = "AspmDisabled"
 165
 166         # PCIE Port 7 Disabled
 167         # PCIE Port 8 Disabled
 168
 169         # PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA
 170         register "PcieRpEnable[8]" = "1"
 171         # Disable CLKREQ#
 172         register "PcieRpClkReqSupport[8]" = "0"
 173         # Use Hot Plug subsystem
 174         register "PcieRpHotPlug[8]" = "1"
 175         # Set MaxPayload to 256 bytes
 176         register "PcieRpMaxPayload[8]" = "RpMaxPayload_256"
 177         # Enable Latency Tolerance Reporting Mechanism
 178         register "PcieRpLtrEnable[8]" = "1"
 179         # Enable Advanced Error Reporting
 180         register "PcieRpAdvancedErrorReporting[8]" = "1"
 181         # Disable Aspm
 182         register "pcie_rp_aspm[8]" = "AspmDisabled"
 183
 184         # USB 2.0 Enable all ports
 185         register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # USB-C Port 2
 186         register "usb2_ports[1]" = "USB2_PORT_MID(OC1)"         # USB3_TYPE-A Port 1
 187         register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"         # USB3_TYPE-A Port 2
 188         register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # USB-C Port 1
 189         register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)"   # M2 Port
 190         register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)"   # Audio board
 191
 192         # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
 193         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 2
 194         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 1
 195         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 2
 196         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 1
 197
 198         register "SsicPortEnable" = "0"
 199
 200         # Must leave UART0 enabled or SD/eMMC will not work as PCI
 201         register "SerialIoDevMode" = "{ \
 202                 [PchSerialIoIndexI2C0]  = PchSerialIoDisabled, \
 203                 [PchSerialIoIndexI2C1]  = PchSerialIoDisabled, \
 204                 [PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
 205                 [PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
 206                 [PchSerialIoIndexI2C4]  = PchSerialIoDisabled, \
 207                 [PchSerialIoIndexI2C5]  = PchSerialIoDisabled, \
 208                 [PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
 209                 [PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
 210                 [PchSerialIoIndexUart0] = PchSerialIoPci, \
 211                 [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
 212                 [PchSerialIoIndexUart2] = PchSerialIoDisabled, \
 213         }"
 214
 215         device cpu_cluster 0 on
 216                 device lapic 0 on end
 217         end
 218         device domain 0 on
 219                 device pci 00.0 on  end # Host Bridge
 220                 device pci 02.0 on  end # Integrated Graphics Device
 221                 device pci 04.0 on  end # Thermal Subsystem
 222                 device pci 08.0 on  end # Gaussian Mixture Model
 223                 device pci 14.0 on  end # USB xHCI
 224                 device pci 14.1 on  end # USB xDCI (OTG)
 225                 device pci 14.2 on  end # Thermal Subsystem
 226                 device pci 16.0 on  end # Management Engine Interface 1
 227                 device pci 17.0 on  end # SATA
 228                 device pci 1c.2 on  end # PCI Express Port 3 x1 baseboard WWAN
 229                 device pci 1c.5 on  end # PCI Express Port 6 x1 baseboard i210
 230                 device pci 1d.0 on  end # PCI Express Port 9 x4 FPGA
 231                 device pci 1e.0 on  end # UART #0
 232                 device pci 1e.4 on  end # eMMC
 233                 device pci 1f.0 on  # LPC Interface
 234                         chip drivers/pc80/tpm
 235                                 device pnp 0c31.0 on end
 236                         end
 237                 end # LPC Bridge
 238                 device pci 1f.1 on  end # P2SB
 239                 device pci 1f.2 on  end # Power Management Controller
 240                 device pci 1f.3 on  end # HDA Controller for HDMI only
 241                 device pci 1f.4 on  end # SMBus
 242                 device pci 1f.5 on  end # PCH SPI
 243                 device pci 1f.6 on  end # GbE
 244         end
 245 end