src/mainboard/gigabyte/ga-d510ud/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <console/console.h>
   5 #include <device/pnp_ops.h>
   6 #include <northbridge/intel/pineview/pineview.h>
   7 #include <southbridge/intel/i82801gx/i82801gx.h>
   8 #include <superio/ite/common/ite.h>
   9 #include <superio/ite/it8720f/it8720f.h>
  10
  11 #define SERIAL_DEV      PNP_DEV(0x2e, IT8720F_SP1)
  12 #define GPIO_DEV        PNP_DEV(0x2e, IT8720F_GPIO)
  13 #define EC_DEV          PNP_DEV(0x2e, IT8720F_EC)
  14
  15 void bootblock_mainboard_early_init(void)
  16 {
  17         /* Set default GPIOs on superio */
  18         pnp_enter_conf_state(GPIO_DEV);
  19
  20         pnp_set_logical_device(GPIO_DEV);
  21         pnp_write_config(GPIO_DEV, 0x25, 0x00);
  22         pnp_write_config(GPIO_DEV, 0x26, 0x0c);
  23         pnp_write_config(GPIO_DEV, 0x28, 0x41);
  24         pnp_write_config(GPIO_DEV, 0x2c, 0x01);
  25         pnp_write_config(GPIO_DEV, 0x62, 0x08);
  26         pnp_write_config(GPIO_DEV, 0x72, 0x00);
  27         pnp_write_config(GPIO_DEV, 0xb8, 0x00);
  28         pnp_write_config(GPIO_DEV, 0xc0, 0x00);
  29         pnp_write_config(GPIO_DEV, 0xc1, 0x0c);
  30         pnp_write_config(GPIO_DEV, 0xc3, 0x41);
  31         pnp_write_config(GPIO_DEV, 0xc8, 0x00);
  32         pnp_write_config(GPIO_DEV, 0xcb, 0x00);
  33         pnp_write_config(GPIO_DEV, 0xe9, 0x01);
  34         pnp_write_config(GPIO_DEV, 0xfc, 0xa4);
  35
  36         pnp_exit_conf_state(GPIO_DEV);
  37
  38         ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  39
  40         pnp_enter_conf_state(GPIO_DEV);
  41         pnp_set_logical_device(GPIO_DEV);
  42
  43         printk(BIOS_DEBUG, "ITE register 0xef: 0x%02x ", pnp_read_config(GPIO_DEV, 0xef));
  44
  45         /* Disable SIO reboot */
  46         pnp_write_config(GPIO_DEV, 0xef, 0x7e);
  47
  48         printk(BIOS_DEBUG, "=> 0x%02x\n", pnp_read_config(GPIO_DEV, 0xef));
  49
  50         pnp_set_logical_device(EC_DEV);
  51         pnp_write_config(EC_DEV, 0x70, 0x00); /* Don't use IRQ9 */
  52         pnp_write_config(EC_DEV, 0x30, 0x01); /* Enable */
  53
  54         pnp_exit_conf_state(GPIO_DEV);
  55 }
  56
  57 void get_mb_spd_addrmap(u8 *spd_addrmap)
  58 {
  59         spd_addrmap[0] = 0x50;
  60         spd_addrmap[1] = 0x51;
  61 }