src/mainboard/gizmosphere/gizmo2/dsdt.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* DefinitionBlock Statement */
   4 #include <acpi/acpi.h>
   5 DefinitionBlock (
   6         "dsdt.aml",
   7         "DSDT",
   8         ACPI_DSDT_REV_2,
   9         OEM_ID,
  10         ACPI_TABLE_CREATOR,
  11         0x00010001      /* OEM Revision */
  12         )
  13 {       /* Start of ASL file */
  14         #include <acpi/dsdt_top.asl>
  15
  16         /* Globals for the platform */
  17         #include "acpi/mainboard.asl"
  18
  19         /* Describe the USB Overcurrent pins */
  20         #include "acpi/usb_oc.asl"
  21
  22         /* PCI IRQ mapping for the Southbridge */
  23         #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
  24
  25         /* Describe the processor tree (\_SB) */
  26         #include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
  27
  28         /* Contains the supported sleep states for this chipset */
  29         #include <southbridge/amd/common/acpi/sleepstates.asl>
  30
  31         /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
  32         #include "acpi/sleep.asl"
  33
  34         /* System Bus */
  35         Scope(\_SB) { /* Start \_SB scope */
  36                 /* global utility methods expected within the \_SB scope */
  37                 #include <arch/x86/acpi/globutil.asl>
  38
  39                 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
  40                 #include "acpi/routing.asl"
  41
  42                 Device(PWRB) {
  43                         Name(_HID, EISAID("PNP0C0C"))
  44                         Name(_UID, 0xAA)
  45                         Name(_PRW, Package () {3, 0x04})
  46                         Name(_STA, 0x0B)
  47                 }
  48
  49                 Device(PCI0) {
  50                         /* Describe the AMD Northbridge */
  51                         #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
  52
  53                         /* Describe the AMD Fusion Controller Hub Southbridge */
  54                         #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
  55                 }
  56
  57                 /* Describe PCI INT[A-H] for the Southbridge */
  58                 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
  59
  60         } /* End \_SB scope */
  61
  62         /* Describe SMBUS for the Southbridge */
  63         #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
  64
  65         /* Define the General Purpose Events for the platform */
  66         #include "acpi/gpe.asl"
  67
  68         /* Define the Thermal zones and methods for the platform */
  69         #include "acpi/thermal.asl"
  70 }
  71 /* End of ASL file */