src/mainboard/gizmosphere/gizmo2/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <southbridge/amd/agesa/hudson/pci_devs.h>
   5 #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h>
   6 #include <southbridge/amd/common/amd_pci_util.h>
   7 #include <northbridge/amd/agesa/family16kb/pci_devs.h>
   8
   9 /***********************************************************
  10  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  11  * This table is responsible for physically routing the PIC and
  12  * IOAPIC IRQs to the different PCI devices on the system.  It
  13  * is read and written via registers 0xC00/0xC01 as an
  14  * Index/Data pair.  These values are chipset and mainboard
  15  * dependent and should be updated accordingly.
  16  *
  17  * These values are used by the PCI configuration space,
  18  * MP Tables.  TODO: Make ACPI use these values too.
  19  */
  20 static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
  21         /* INTA# - INTH# */
  22         [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
  23         /* Misc-nil,0,1,2, INT from Serial irq */
  24         [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  25         /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
  26         [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
  27         /* IMC INT0 - 5 */
  28         [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
  29         /* USB Devs 18/19/22 INTA-C */
  30         [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
  31         /* SATA */
  32         [0x41] = 0x0F,
  33 };
  34
  35 static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
  36         /* INTA# - INTH# */
  37         [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
  38         /* Misc-nil,0,1,2, INT from Serial irq */
  39         [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  40         /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
  41         [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,
  42         /* IMC INT0 - 5 */
  43         [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,
  44         /* USB Devs 18/19/20/22 INTA-C */
  45         [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
  46         /* SATA */
  47         [0x41] = 0x13
  48 };
  49
  50 /*
  51  * This table defines the index into the picr/intr_data
  52  * tables for each device.  Any enabled device and slot
  53  * that uses hardware interrupts should have an entry
  54  * in this table to define its index into the FCH
  55  * PCI_INTR register 0xC00/0xC01.  This index will define
  56  * the interrupt that it should use.  Putting PIRQ_A into
  57  * the PIN A index for a device will tell that device to
  58  * use PIC IRQ 10 if it uses PIN A for its hardware INT.
  59  */
  60 static const struct pirq_struct mainboard_pirq_data[] = {
  61         /* {PCI_devfn,  {PIN A, PIN B, PIN C, PIN D}}, */
  62         {GFX_DEVFN,     {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}},                   /* VGA:         01.0 */
  63         {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}},                       /* Audio:       01.1 */
  64         {NB_PCIE_PORT1_DEVFN,   {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},      /* x4 PCIe:     02.1 */
  65         {NB_PCIE_PORT2_DEVFN,   {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}},      /* mPCIe:       02.2 */
  66         {NB_PCIE_PORT3_DEVFN,   {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}},      /* NIC:         02.3 */
  67         {NB_PCIE_PORT4_DEVFN,   {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}},      /* Edge:        02.4 */
  68         {NB_PCIE_PORT5_DEVFN,   {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}},      /* Edge:        02.5 */
  69         {XHCI_DEVFN,    {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}},           /* XHCI:        10.0 */
  70         {SATA_DEVFN,    {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},        /* SATA:        11.0 */
  71         {OHCI1_DEVFN,   {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}},       /* OHCI1:       12.0 */
  72         {EHCI1_DEVFN,   {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}},       /* EHCI1:       12.2 */
  73         {OHCI2_DEVFN,   {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}},       /* OHCI2:       13.0 */
  74         {EHCI2_DEVFN,   {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}},       /* EHCI2:       13.2 */
  75         {SMBUS_DEVFN,   {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}},       /* SMBUS:       14.0 */
  76         {HDA_DEVFN,             {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},         /* HDA:         14.2 */
  77         {SD_DEVFN,              {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}},          /* SD:          14.7 */
  78 };
  79
  80 /* PIRQ Setup */
  81 static void pirq_setup(void)
  82 {
  83         pirq_data_ptr = mainboard_pirq_data;
  84         pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
  85         intr_data_ptr = mainboard_intr_data;
  86         picr_data_ptr = mainboard_picr_data;
  87 }
  88
  89 /**********************************************
  90  * enable the dedicated function in mainboard.
  91  **********************************************/
  92 static void mainboard_enable(struct device *dev)
  93 {
  94         /* Initialize the PIRQ data structures for consumption */
  95         pirq_setup();
  96 }
  97
  98 struct chip_operations mainboard_ops = {
  99         .enable_dev = mainboard_enable,
 100 };