1 /* SPDX-License-Identifier: GPL-2.0-only */
7 #include <console/console.h>
8 #include <device/mmio.h>
10 #include <device/device.h>
11 #include <device/i2c_simple.h>
12 #include <ec/google/chromeec/ec.h>
14 #include <soc/clock.h>
15 #include <soc/display.h>
24 #include <arm-trusted-firmware/include/export/plat/rockchip/common/plat_params_exp.h>
27 * We have to drive the stronger pull-up within 1 second of powering up the
28 * touchpad to prevent its firmware from falling into recovery. Not on
29 * Scarlet-based boards.
31 static void configure_touchpad(void)
33 gpio_output(GPIO_TP_RST_L
, 1); /* TP's I2C pull-up rail */
37 * Wifi's PDN/RST line is pulled down by its (unpowered) voltage rails, but
38 * this reset pin is pulled up by default. Let's drive it low as early as we
39 * can. This only applies to boards with Marvell 8997 WiFi.
41 static void assert_wifi_reset(void)
43 gpio_output(GPIO_WLAN_RST_L
, 0); /* Assert WLAN_MODULE_RST# */
46 static void configure_emmc(void)
48 /* Host controller does not support programmable clock generator.
49 * If we don't do this setting, when we use phy to control the
50 * emmc clock(when clock exceed 50MHz), it will get wrong clock.
52 * Refer to TRM V0.3 Part 1 Chapter 15 PAGE 782 for this register.
53 * Please search "_CON11[7:0]" to locate register description.
55 write32(&rk3399_grf
->emmccore_con
[11], RK_CLRSETBITS(0xff, 0));
57 rkclk_configure_emmc();
60 static void register_apio_suspend(void)
62 static struct bl_aux_param_rk_apio param_apio
= {
64 .type
= BL_AUX_PARAM_RK_SUSPEND_APIO
,
74 register_bl31_aux_param(¶m_apio
.h
);
77 static void register_gpio_suspend(void)
80 * These three GPIO params are used to shut down the 1.5V, 1.8V and
81 * 3.3V power rails, which need to be shut down ordered by voltage,
82 * with highest voltage first.
83 * Since register_bl31() appends to the front of the list, we need to
84 * register them backwards, with 1.5V coming first.
85 * 1.5V and 1.8V are EC-controlled on Scarlet derivatives,
88 if (!CONFIG(GRU_BASEBOARD_SCARLET
)) {
89 static struct bl_aux_param_gpio param_p15_en
= {
90 .h
= { .type
= BL_AUX_PARAM_RK_SUSPEND_GPIO
},
91 .gpio
= { .polarity
= ARM_TF_GPIO_LEVEL_LOW
},
93 param_p15_en
.gpio
.index
= GPIO_P15V_EN
.raw
;
94 register_bl31_aux_param(¶m_p15_en
.h
);
96 static struct bl_aux_param_gpio param_p18_audio_en
= {
97 .h
= { .type
= BL_AUX_PARAM_RK_SUSPEND_GPIO
},
98 .gpio
= { .polarity
= ARM_TF_GPIO_LEVEL_LOW
},
100 param_p18_audio_en
.gpio
.index
= GPIO_P18V_AUDIO_PWREN
.raw
;
101 register_bl31_aux_param(¶m_p18_audio_en
.h
);
104 static struct bl_aux_param_gpio param_p30_en
= {
105 .h
= { .type
= BL_AUX_PARAM_RK_SUSPEND_GPIO
},
106 .gpio
= { .polarity
= ARM_TF_GPIO_LEVEL_LOW
},
108 param_p30_en
.gpio
.index
= GPIO_P30V_EN
.raw
;
109 register_bl31_aux_param(¶m_p30_en
.h
);
112 static void register_reset_to_bl31(void)
114 static struct bl_aux_param_gpio param_reset
= {
116 .type
= BL_AUX_PARAM_RK_RESET_GPIO
,
123 /* gru/kevin reset pin: gpio0b3 */
124 param_reset
.gpio
.index
= GPIO_RESET
.raw
;
126 register_bl31_aux_param(¶m_reset
.h
);
129 static void register_poweroff_to_bl31(void)
131 static struct bl_aux_param_gpio param_poweroff
= {
133 .type
= BL_AUX_PARAM_RK_POWEROFF_GPIO
,
141 * gru/kevin power off pin: gpio1a6,
142 * reuse with tsadc int pin, so iomux need set back to
143 * gpio in BL31 and depthcharge before you setting this gpio
145 param_poweroff
.gpio
.index
= GPIO_POWEROFF
.raw
;
147 register_bl31_aux_param(¶m_poweroff
.h
);
150 static void configure_sdmmc(void)
152 gpio_output(GPIO(2, A
, 2), 1); /* SDMMC_SDIO_PWR_EN */
154 /* set SDMMC_DET_L pin */
155 if (CONFIG(GRU_BASEBOARD_SCARLET
))
157 * do not have external pull up, so need to
158 * set this pin internal pull up
160 gpio_input_pullup(GPIO(1, B
, 3));
162 gpio_input(GPIO(4, D
, 0));
165 * Keep sd card io domain 3v
166 * In Scarlet derivatives, this GPIO set to high will get 3v,
167 * With other board variants setting this GPIO low results in 3V.
169 if (CONFIG(GRU_BASEBOARD_SCARLET
))
170 gpio_output(GPIO(2, D
, 4), 1);
172 gpio_output(GPIO(2, D
, 4), 0);
174 gpio_input(GPIO(4, B
, 0)); /* SDMMC0_D0 remove pull-up */
175 gpio_input(GPIO(4, B
, 1)); /* SDMMC0_D1 remove pull-up */
176 gpio_input(GPIO(4, B
, 2)); /* SDMMC0_D2 remove pull-up */
177 gpio_input(GPIO(4, B
, 3)); /* SDMMC0_D3 remove pull-up */
178 gpio_input(GPIO(4, B
, 4)); /* SDMMC0_CLK remove pull-down */
179 gpio_input(GPIO(4, B
, 5)); /* SDMMC0_CMD remove pull-up */
181 write32(&rk3399_grf
->gpio2_p
[2][1], RK_CLRSETBITS(0xfff, 0));
184 * Set all outputs' drive strength to 8 mA. Group 4 bank B driver
185 * strength requires three bits per pin. Value of 2 written in that
186 * three bit field means '8 mA', as deduced from the kernel code.
188 * Thus the six pins involved in SDMMC interface require 18 bits to
189 * configure drive strength, but each 32 bit register provides only 16
190 * bits for this setting, this covers 5 pins fully and one bit from
191 * the 6th pin. Two more bits spill over to the next register. This is
192 * described on page 378 of rk3399 TRM Version 0.3 Part 1.
194 write32(&rk3399_grf
->gpio4b_e01
,
195 RK_CLRSETBITS(0xffff,
196 (2 << 0) | (2 << 3) |
197 (2 << 6) | (2 << 9) | (2 << 12)));
198 write32(&rk3399_grf
->gpio4b_e2
, RK_CLRSETBITS(3, 1));
200 /* And now set the multiplexor to enable SDMMC0. */
201 write32(&rk3399_grf
->iomux_sdmmc
, IOMUX_SDMMC
);
204 static void configure_codec(void)
206 gpio_input(GPIO(3, D
, 0)); /* I2S0_SCLK remove pull-up */
207 gpio_input(GPIO(3, D
, 1)); /* I2S0_RX remove pull-up */
208 gpio_input(GPIO(3, D
, 2)); /* I2S0_TX remove pull-up */
209 gpio_input(GPIO(3, D
, 3)); /* I2S0_SDI0 remove pull-up */
210 /* GPIOs 3_D4 - 3_D6 not used for I2S and are SKU ID pins on Scarlet. */
211 gpio_input(GPIO(3, D
, 7)); /* I2S0_SDO0 remove pull-up */
212 gpio_input(GPIO(4, A
, 0)); /* I2S0_MCLK remove pull-up */
214 write32(&rk3399_grf
->iomux_i2s0
, IOMUX_I2S0_SD0
);
215 write32(&rk3399_grf
->iomux_i2sclk
, IOMUX_I2SCLK
);
217 if (!CONFIG(GRU_BASEBOARD_SCARLET
))
218 gpio_output(GPIO_P18V_AUDIO_PWREN
, 1);
219 gpio_output(GPIO_SPK_PA_EN
, 0);
221 rkclk_configure_i2s(12288000);
224 static void configure_display(void)
227 * Rainier is Scarlet-derived, but uses EDP so use board-specific
228 * config rather than baseboard.
230 if (CONFIG(BOARD_GOOGLE_SCARLET
)) {
231 gpio_output(GPIO(4, D
, 1), 0); /* DISPLAY_RST_L */
232 gpio_output(GPIO(4, D
, 3), 1); /* PPVARP_LCD */
234 gpio_output(GPIO(4, D
, 4), 1); /* PPVARN_LCD */
235 mdelay(20 + 2); /* add 2ms for bias rise time */
236 gpio_output(GPIO(4, D
, 1), 1); /* DISPLAY_RST_L */
239 /* set pinmux for edp HPD */
240 gpio_input_pulldown(GPIO(4, C
, 7));
241 write32(&rk3399_grf
->iomux_edp_hotplug
, IOMUX_EDP_HOTPLUG
);
243 gpio_output(GPIO(4, D
, 3), 1); /* P3.3V_DISP */
247 static void usb_power_cycle(int port
)
249 if (google_chromeec_set_usb_pd_role(port
, USB_PD_CTRL_ROLE_FORCE_SINK
))
250 printk(BIOS_ERR
, "Cannot force USB%d PD sink\n", port
);
252 mdelay(10); /* Make sure USB stick is fully depowered. */
254 if (google_chromeec_set_usb_pd_role(port
, USB_PD_CTRL_ROLE_TOGGLE_ON
))
255 printk(BIOS_ERR
, "Cannot restore USB%d PD mode\n", port
);
258 static void setup_usb(int port
)
260 /* Must be PHY0 or PHY1. */
261 assert(port
== 0 || port
== 1);
264 * A few magic PHY tuning values that improve eye diagram amplitude
265 * and make it extra sure we get reliable communication in firmware
266 * Set max ODT compensation voltage and current tuning reference.
268 write32(&rk3399_grf
->usbphy_ctrl
[port
][3], RK_CLRSETBITS(0xfff, 0x2e3));
270 /* Set max pre-emphasis level on PHY0 and PHY1. */
271 write32(&rk3399_grf
->usbphy_ctrl
[port
][12],
272 RK_CLRSETBITS(0xffff, 0xa7));
275 * 1. Disable the pre-emphasize in eop state and chirp
276 * state to avoid mis-trigger the disconnect detection
277 * and also avoid high-speed handshake fail for PHY0
278 * and PHY1 consist of otg-port and host-port.
280 * 2. Configure PHY0 and PHY1 otg-ports squelch detection
281 * threshold to 125mV (default is 150mV).
283 write32(&rk3399_grf
->usbphy_ctrl
[port
][0],
284 RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13));
285 write32(&rk3399_grf
->usbphy_ctrl
[port
][13], RK_CLRBITS(3 << 0));
288 * ODT auto compensation bypass, and set max driver
289 * strength only for PHY0 and PHY1 otg-port.
291 write32(&rk3399_grf
->usbphy_ctrl
[port
][2],
292 RK_CLRSETBITS(0x7e << 4, 0x60 << 4));
295 * ODT auto refresh bypass, and set the max bias current
296 * tuning reference only for PHY0 and PHY1 otg-port.
298 write32(&rk3399_grf
->usbphy_ctrl
[port
][3],
299 RK_CLRSETBITS(0x21c, 1 << 4));
302 * ODT auto compensation bypass, and set default driver
303 * strength only for PHY0 and PHY1 host-port.
305 write32(&rk3399_grf
->usbphy_ctrl
[port
][15], RK_SETBITS(1 << 10));
307 /* ODT auto refresh bypass only for PHY0 and PHY1 host-port. */
308 write32(&rk3399_grf
->usbphy_ctrl
[port
][16], RK_CLRBITS(1 << 9));
316 * Need to power-cycle USB ports for use in firmware, since some devices
317 * can't fall back to USB 2.0 after they saw SuperSpeed terminations.
318 * This takes about a dozen milliseconds, so only do it in boot modes
319 * that have firmware UI (which one could select USB boot from).
321 if (display_init_required())
322 usb_power_cycle(port
);
325 static void mainboard_init(struct device
*dev
)
330 if (display_init_required())
333 if (CONFIG(GRU_HAS_WLAN_RESET
))
335 if (!CONFIG(GRU_BASEBOARD_SCARLET
)) {
336 configure_touchpad(); /* Scarlet: works differently */
337 setup_usb(1); /* Scarlet: only one USB port */
339 register_gpio_suspend();
340 register_reset_to_bl31();
341 register_poweroff_to_bl31();
342 register_apio_suspend();
345 static void prepare_backlight_i2c(void)
347 gpio_input(GPIO(1, B
, 7)); /* I2C0_SDA remove pull_up */
348 gpio_input(GPIO(1, C
, 0)); /* I2C0_SCL remove pull_up */
350 i2c_init(0, 100*KHz
);
352 write32(&rk3399_pmugrf
->iomux_i2c0_sda
, IOMUX_I2C0_SDA
);
353 write32(&rk3399_pmugrf
->iomux_i2c0_scl
, IOMUX_I2C0_SCL
);
356 void mainboard_power_on_backlight(void)
358 gpio_output(GPIO_BL_EN
, 1); /* BL_EN */
360 /* Configure as output GPIO, to be toggled by payload. */
361 if (CONFIG(GRU_BASEBOARD_SCARLET
))
362 gpio_output(GPIO_BACKLIGHT
, 0);
364 if (CONFIG(BOARD_GOOGLE_GRU
))
365 prepare_backlight_i2c();
368 static struct panel_init_command innolux_p097pfg_init_cmds
[] = {
370 MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00),
371 MIPI_INIT_CMD(0xB1, 0xE8, 0x11),
372 MIPI_INIT_CMD(0xB2, 0x25, 0x02),
373 MIPI_INIT_CMD(0xB5, 0x08, 0x00),
374 MIPI_INIT_CMD(0xBC, 0x0F, 0x00),
375 MIPI_INIT_CMD(0xB8, 0x03, 0x06, 0x00, 0x00),
376 MIPI_INIT_CMD(0xBD, 0x01, 0x90, 0x14, 0x14),
377 MIPI_INIT_CMD(0x6F, 0x01),
378 MIPI_INIT_CMD(0xC0, 0x03),
379 MIPI_INIT_CMD(0x6F, 0x02),
380 MIPI_INIT_CMD(0xC1, 0x0D),
381 MIPI_INIT_CMD(0xD9, 0x01, 0x09, 0x70),
382 MIPI_INIT_CMD(0xC5, 0x12, 0x21, 0x00),
383 MIPI_INIT_CMD(0xBB, 0x93, 0x93),
386 MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01),
387 MIPI_INIT_CMD(0xB3, 0x3C, 0x3C),
388 MIPI_INIT_CMD(0xB4, 0x0F, 0x0F),
389 MIPI_INIT_CMD(0xB9, 0x45, 0x45),
390 MIPI_INIT_CMD(0xBA, 0x14, 0x14),
391 MIPI_INIT_CMD(0xCA, 0x02),
392 MIPI_INIT_CMD(0xCE, 0x04),
393 MIPI_INIT_CMD(0xC3, 0x9B, 0x9B),
394 MIPI_INIT_CMD(0xD8, 0xC0, 0x03),
395 MIPI_INIT_CMD(0xBC, 0x82, 0x01),
396 MIPI_INIT_CMD(0xBD, 0x9E, 0x01),
399 MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02),
400 MIPI_INIT_CMD(0xB0, 0x82),
401 MIPI_INIT_CMD(0xD1, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x82, 0x00, 0xA5,
402 0x00, 0xC1, 0x00, 0xEA, 0x01, 0x0D, 0x01, 0x40),
403 MIPI_INIT_CMD(0xD2, 0x01, 0x6A, 0x01, 0xA8, 0x01, 0xDC, 0x02, 0x29,
404 0x02, 0x67, 0x02, 0x68, 0x02, 0xA8, 0x02, 0xF0),
405 MIPI_INIT_CMD(0xD3, 0x03, 0x19, 0x03, 0x49, 0x03, 0x67, 0x03, 0x8C,
406 0x03, 0xA6, 0x03, 0xC7, 0x03, 0xDE, 0x03, 0xEC),
407 MIPI_INIT_CMD(0xD4, 0x03, 0xFF, 0x03, 0xFF),
408 MIPI_INIT_CMD(0xE0, 0x00, 0x00, 0x00, 0x86, 0x00, 0xC5, 0x00, 0xE5,
409 0x00, 0xFF, 0x01, 0x26, 0x01, 0x45, 0x01, 0x75),
410 MIPI_INIT_CMD(0xE1, 0x01, 0x9C, 0x01, 0xD5, 0x02, 0x05, 0x02, 0x4D,
411 0x02, 0x86, 0x02, 0x87, 0x02, 0xC3, 0x03, 0x03),
412 MIPI_INIT_CMD(0xE2, 0x03, 0x2A, 0x03, 0x56, 0x03, 0x72, 0x03, 0x94,
413 0x03, 0xAC, 0x03, 0xCB, 0x03, 0xE0, 0x03, 0xED),
414 MIPI_INIT_CMD(0xE3, 0x03, 0xFF, 0x03, 0xFF),
417 MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03),
418 MIPI_INIT_CMD(0xB0, 0x00, 0x00, 0x00, 0x00),
419 MIPI_INIT_CMD(0xB1, 0x00, 0x00, 0x00, 0x00),
420 MIPI_INIT_CMD(0xB2, 0x00, 0x00, 0x06, 0x04, 0x01, 0x40, 0x85),
421 MIPI_INIT_CMD(0xB3, 0x10, 0x07, 0xFC, 0x04, 0x01, 0x40, 0x80),
422 MIPI_INIT_CMD(0xB6, 0xF0, 0x08, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01,
424 MIPI_INIT_CMD(0xBA, 0xC5, 0x07, 0x00, 0x04, 0x11, 0x25, 0x8C),
425 MIPI_INIT_CMD(0xBB, 0xC5, 0x07, 0x00, 0x03, 0x11, 0x25, 0x8C),
426 MIPI_INIT_CMD(0xC0, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x80),
427 MIPI_INIT_CMD(0xC1, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x80),
428 MIPI_INIT_CMD(0xC4, 0x00, 0x00),
429 MIPI_INIT_CMD(0xEF, 0x41),
432 MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x04),
433 MIPI_INIT_CMD(0xEC, 0x4C),
436 MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05),
437 MIPI_INIT_CMD(0xB0, 0x13, 0x03, 0x03, 0x01),
438 MIPI_INIT_CMD(0xB1, 0x30, 0x00),
439 MIPI_INIT_CMD(0xB2, 0x02, 0x02, 0x00),
440 MIPI_INIT_CMD(0xB3, 0x82, 0x23, 0x82, 0x9D),
441 MIPI_INIT_CMD(0xB4, 0xC5, 0x75, 0x24, 0x57),
442 MIPI_INIT_CMD(0xB5, 0x00, 0xD4, 0x72, 0x11, 0x11, 0xAB, 0x0A),
443 MIPI_INIT_CMD(0xB6, 0x00, 0x00, 0xD5, 0x72, 0x24, 0x56),
444 MIPI_INIT_CMD(0xB7, 0x5C, 0xDC, 0x5C, 0x5C),
445 MIPI_INIT_CMD(0xB9, 0x0C, 0x00, 0x00, 0x01, 0x00),
446 MIPI_INIT_CMD(0xC0, 0x75, 0x11, 0x11, 0x54, 0x05),
447 MIPI_INIT_CMD(0xC6, 0x00, 0x00, 0x00, 0x00),
448 MIPI_INIT_CMD(0xD0, 0x00, 0x48, 0x08, 0x00, 0x00),
449 MIPI_INIT_CMD(0xD1, 0x00, 0x48, 0x09, 0x00, 0x00),
452 MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06),
453 MIPI_INIT_CMD(0xB0, 0x02, 0x32, 0x32, 0x08, 0x2F),
454 MIPI_INIT_CMD(0xB1, 0x2E, 0x15, 0x14, 0x13, 0x12),
455 MIPI_INIT_CMD(0xB2, 0x11, 0x10, 0x00, 0x3D, 0x3D),
456 MIPI_INIT_CMD(0xB3, 0x3D, 0x3D, 0x3D, 0x3D, 0x3D),
457 MIPI_INIT_CMD(0xB4, 0x3D, 0x32),
458 MIPI_INIT_CMD(0xB5, 0x03, 0x32, 0x32, 0x09, 0x2F),
459 MIPI_INIT_CMD(0xB6, 0x2E, 0x1B, 0x1A, 0x19, 0x18),
460 MIPI_INIT_CMD(0xB7, 0x17, 0x16, 0x01, 0x3D, 0x3D),
461 MIPI_INIT_CMD(0xB8, 0x3D, 0x3D, 0x3D, 0x3D, 0x3D),
462 MIPI_INIT_CMD(0xB9, 0x3D, 0x32),
463 MIPI_INIT_CMD(0xC0, 0x01, 0x32, 0x32, 0x09, 0x2F),
464 MIPI_INIT_CMD(0xC1, 0x2E, 0x1A, 0x1B, 0x16, 0x17),
465 MIPI_INIT_CMD(0xC2, 0x18, 0x19, 0x03, 0x3D, 0x3D),
466 MIPI_INIT_CMD(0xC3, 0x3D, 0x3D, 0x3D, 0x3D, 0x3D),
467 MIPI_INIT_CMD(0xC4, 0x3D, 0x32),
468 MIPI_INIT_CMD(0xC5, 0x00, 0x32, 0x32, 0x08, 0x2F),
469 MIPI_INIT_CMD(0xC6, 0x2E, 0x14, 0x15, 0x10, 0x11),
470 MIPI_INIT_CMD(0xC7, 0x12, 0x13, 0x02, 0x3D, 0x3D),
471 MIPI_INIT_CMD(0xC8, 0x3D, 0x3D, 0x3D, 0x3D, 0x3D),
472 MIPI_INIT_CMD(0xC9, 0x3D, 0x32),
477 static struct panel_init_command kd097d04_init_commands
[] = {
478 /* voltage setting */
479 MIPI_INIT_CMD(0xB0, 0x00),
480 MIPI_INIT_CMD(0xB2, 0x02),
481 MIPI_INIT_CMD(0xB3, 0x11),
482 MIPI_INIT_CMD(0xB4, 0x00),
483 MIPI_INIT_CMD(0xB6, 0x80),
485 MIPI_INIT_CMD(0xB7, 0x02),
486 MIPI_INIT_CMD(0xB8, 0x80),
487 MIPI_INIT_CMD(0xBA, 0x43),
489 MIPI_INIT_CMD(0xBB, 0x53),
491 MIPI_INIT_CMD(0xBC, 0x0A),
493 MIPI_INIT_CMD(0xBD, 0x4A),
495 MIPI_INIT_CMD(0xBE, 0x2F),
497 MIPI_INIT_CMD(0xBF, 0x1A),
498 MIPI_INIT_CMD(0xF0, 0x39),
499 MIPI_INIT_CMD(0xF1, 0x22),
501 MIPI_INIT_CMD(0xB0, 0x02),
502 MIPI_INIT_CMD(0xC0, 0x00),
503 MIPI_INIT_CMD(0xC1, 0x01),
504 MIPI_INIT_CMD(0xC2, 0x0B),
505 MIPI_INIT_CMD(0xC3, 0x15),
506 MIPI_INIT_CMD(0xC4, 0x22),
507 MIPI_INIT_CMD(0xC5, 0x11),
508 MIPI_INIT_CMD(0xC6, 0x15),
509 MIPI_INIT_CMD(0xC7, 0x19),
510 MIPI_INIT_CMD(0xC8, 0x1A),
511 MIPI_INIT_CMD(0xC9, 0x16),
512 MIPI_INIT_CMD(0xCA, 0x18),
513 MIPI_INIT_CMD(0xCB, 0x13),
514 MIPI_INIT_CMD(0xCC, 0x18),
515 MIPI_INIT_CMD(0xCD, 0x13),
516 MIPI_INIT_CMD(0xCE, 0x1C),
517 MIPI_INIT_CMD(0xCF, 0x19),
518 MIPI_INIT_CMD(0xD0, 0x21),
519 MIPI_INIT_CMD(0xD1, 0x2C),
520 MIPI_INIT_CMD(0xD2, 0x2F),
521 MIPI_INIT_CMD(0xD3, 0x30),
522 MIPI_INIT_CMD(0xD4, 0x19),
523 MIPI_INIT_CMD(0xD5, 0x1F),
524 MIPI_INIT_CMD(0xD6, 0x00),
525 MIPI_INIT_CMD(0xD7, 0x01),
526 MIPI_INIT_CMD(0xD8, 0x0B),
527 MIPI_INIT_CMD(0xD9, 0x15),
528 MIPI_INIT_CMD(0xDA, 0x22),
529 MIPI_INIT_CMD(0xDB, 0x11),
530 MIPI_INIT_CMD(0xDC, 0x15),
531 MIPI_INIT_CMD(0xDD, 0x19),
532 MIPI_INIT_CMD(0xDE, 0x1A),
533 MIPI_INIT_CMD(0xDF, 0x16),
534 MIPI_INIT_CMD(0xE0, 0x18),
535 MIPI_INIT_CMD(0xE1, 0x13),
536 MIPI_INIT_CMD(0xE2, 0x18),
537 MIPI_INIT_CMD(0xE3, 0x13),
538 MIPI_INIT_CMD(0xE4, 0x1C),
539 MIPI_INIT_CMD(0xE5, 0x19),
540 MIPI_INIT_CMD(0xE6, 0x21),
541 MIPI_INIT_CMD(0xE7, 0x2C),
542 MIPI_INIT_CMD(0xE8, 0x2F),
543 MIPI_INIT_CMD(0xE9, 0x30),
544 MIPI_INIT_CMD(0xEA, 0x19),
545 MIPI_INIT_CMD(0xEB, 0x1F),
546 /* GOA MUX setting */
547 MIPI_INIT_CMD(0xB0, 0x01),
548 MIPI_INIT_CMD(0xC0, 0x10),
549 MIPI_INIT_CMD(0xC1, 0x0F),
550 MIPI_INIT_CMD(0xC2, 0x0E),
551 MIPI_INIT_CMD(0xC3, 0x0D),
552 MIPI_INIT_CMD(0xC4, 0x0C),
553 MIPI_INIT_CMD(0xC5, 0x0B),
554 MIPI_INIT_CMD(0xC6, 0x0A),
555 MIPI_INIT_CMD(0xC7, 0x09),
556 MIPI_INIT_CMD(0xC8, 0x08),
557 MIPI_INIT_CMD(0xC9, 0x07),
558 MIPI_INIT_CMD(0xCA, 0x06),
559 MIPI_INIT_CMD(0xCB, 0x05),
560 MIPI_INIT_CMD(0xCC, 0x00),
561 MIPI_INIT_CMD(0xCD, 0x01),
562 MIPI_INIT_CMD(0xCE, 0x02),
563 MIPI_INIT_CMD(0xCF, 0x03),
564 MIPI_INIT_CMD(0xD0, 0x04),
565 MIPI_INIT_CMD(0xD6, 0x10),
566 MIPI_INIT_CMD(0xD7, 0x0F),
567 MIPI_INIT_CMD(0xD8, 0x0E),
568 MIPI_INIT_CMD(0xD9, 0x0D),
569 MIPI_INIT_CMD(0xDA, 0x0C),
570 MIPI_INIT_CMD(0xDB, 0x0B),
571 MIPI_INIT_CMD(0xDC, 0x0A),
572 MIPI_INIT_CMD(0xDD, 0x09),
573 MIPI_INIT_CMD(0xDE, 0x08),
574 MIPI_INIT_CMD(0xDF, 0x07),
575 MIPI_INIT_CMD(0xE0, 0x06),
576 MIPI_INIT_CMD(0xE1, 0x05),
577 MIPI_INIT_CMD(0xE2, 0x00),
578 MIPI_INIT_CMD(0xE3, 0x01),
579 MIPI_INIT_CMD(0xE4, 0x02),
580 MIPI_INIT_CMD(0xE5, 0x03),
581 MIPI_INIT_CMD(0xE6, 0x04),
582 MIPI_INIT_CMD(0xE7, 0x00),
583 MIPI_INIT_CMD(0xEC, 0xC0),
584 /* GOA timing setting */
585 MIPI_INIT_CMD(0xB0, 0x03),
586 MIPI_INIT_CMD(0xC0, 0x01),
587 MIPI_INIT_CMD(0xC2, 0x6F),
588 MIPI_INIT_CMD(0xC3, 0x6F),
589 MIPI_INIT_CMD(0xC5, 0x36),
590 MIPI_INIT_CMD(0xC8, 0x08),
591 MIPI_INIT_CMD(0xC9, 0x04),
592 MIPI_INIT_CMD(0xCA, 0x41),
593 MIPI_INIT_CMD(0xCC, 0x43),
594 MIPI_INIT_CMD(0xCF, 0x60),
595 MIPI_INIT_CMD(0xD2, 0x04),
596 MIPI_INIT_CMD(0xD3, 0x04),
597 MIPI_INIT_CMD(0xD4, 0x03),
598 MIPI_INIT_CMD(0xD5, 0x02),
599 MIPI_INIT_CMD(0xD6, 0x01),
600 MIPI_INIT_CMD(0xD7, 0x00),
601 MIPI_INIT_CMD(0xDB, 0x01),
602 MIPI_INIT_CMD(0xDE, 0x36),
603 MIPI_INIT_CMD(0xE6, 0x6F),
604 MIPI_INIT_CMD(0xE7, 0x6F),
606 MIPI_INIT_CMD(0xB0, 0x06),
607 MIPI_INIT_CMD(0xB8, 0xA5),
608 MIPI_INIT_CMD(0xC0, 0xA5),
609 MIPI_INIT_CMD(0xD5, 0x3F),
613 const struct mipi_panel_data kd097d04_panel
= {
615 .format
= MIPI_DSI_FMT_RGB888
,
617 .display_on_udelay
= 120000,
618 .video_mode_udelay
= 5000,
619 .init_cmd
= kd097d04_init_commands
,
622 static const struct edid_mode kd097d04_edid_mode
= {
623 .name
= "1536x2048@60Hz",
624 .pixel_clock
= 216000,
636 const struct mipi_panel_data inx097pfg_panel
= {
638 .format
= MIPI_DSI_FMT_RGB888
,
640 .display_on_udelay
= 120000,
641 .video_mode_udelay
= 5000,
642 .init_cmd
= innolux_p097pfg_init_cmds
,
645 static const struct edid_mode inx097pfg_edid_mode
= {
646 .name
= "1536x2048@60Hz",
647 .pixel_clock
= 220000,
659 const struct mipi_panel_data
*mainboard_get_mipi_mode
660 (struct edid_mode
*edid_mode
)
667 memcpy(edid_mode
, &inx097pfg_edid_mode
,
668 sizeof(struct edid_mode
));
669 return &inx097pfg_panel
;
675 memcpy(edid_mode
, &kd097d04_edid_mode
,
676 sizeof(struct edid_mode
));
677 return &kd097d04_panel
;
681 static void mainboard_enable(struct device
*dev
)
683 dev
->ops
->init
= &mainboard_init
;
686 struct chip_operations mainboard_ops
= {
687 .enable_dev
= mainboard_enable
,