payloads/edk2: Disable the CPU Timer Lib unless supported
[coreboot.git] / src / mainboard / google / sarien / Kconfig
blob524025369d1f776f90fb83aebe087cf77d38bf8d
1 config BOARD_GOOGLE_BASEBOARD_SARIEN
2         def_bool n
3         select BOARD_ROMSIZE_KB_32768
4         select DRIVERS_GENERIC_BH720
5         select DRIVERS_I2C_GENERIC
6         select DRIVERS_I2C_HID
7         select DRIVERS_SPI_ACPI
8         select DRIVERS_USB_ACPI
9         select EC_GOOGLE_WILCO
10         select GOOGLE_SMBIOS_MAINBOARD_VERSION
11         select HAVE_ACPI_RESUME
12         select HAVE_ACPI_TABLES
13         select I2C_TPM
14         select INTEL_GMA_HAVE_VBT
15         select INTEL_LPSS_UART_FOR_CONSOLE
16         select MAINBOARD_HAS_CHROMEOS
17         select MAINBOARD_HAS_TPM2
18         select MAINBOARD_USES_IFD_EC_REGION
19         select SMBIOS_SERIAL_FROM_VPD if VPD
20         select SOC_INTEL_COMMON_BLOCK_HDA_VERB
21         select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE
22         select SOC_INTEL_WHISKEYLAKE
23         select SPD_READ_BY_WORD
24         select TPM_GOOGLE_CR50
26 config BOARD_GOOGLE_ARCADA
27         select BOARD_GOOGLE_BASEBOARD_SARIEN
28         select DRIVERS_INTEL_ISH
29         select SYSTEM_TYPE_CONVERTIBLE
31 config BOARD_GOOGLE_SARIEN
32         select BOARD_GOOGLE_BASEBOARD_SARIEN
33         select MAINBOARD_USES_IFD_GBE_REGION
34         select SYSTEM_TYPE_LAPTOP
36 if BOARD_GOOGLE_BASEBOARD_SARIEN
38 config CHROMEOS_WIFI_SAR
39         bool "Enable SAR options for ChromeOS build"
40         depends on CHROMEOS
41         default y if CHROMEOS
42         select SAR_ENABLE
43         select USE_SAR
45 config DISABLE_HECI1_AT_PRE_BOOT
46         default y
48 config CHROMEOS
49         select GBB_FLAG_FORCE_DEV_SWITCH_ON
50         select GBB_FLAG_FORCE_DEV_BOOT_USB
51         select GBB_FLAG_FORCE_DEV_BOOT_ALTFW
52         select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
54 config DIMM_MAX
55         default 2
57 config DRIVER_TPM_I2C_BUS
58         hex
59         default 0x4
61 config DRIVER_TPM_I2C_ADDR
62         hex
63         default 0x50
65 config TPM_TIS_ACPI_INTERRUPT
66         int
67         default 82  # GPE0_DW2_18 (GPP_D18)
69 config POWER_OFF_ON_CR50_UPDATE
70         bool
71         default n
73 config MAINBOARD_DIR
74         default "google/sarien"
76 config MAINBOARD_FAMILY
77         string
78         default "Google_Arcada" if BOARD_GOOGLE_ARCADA
79         default "Google_Sarien" if BOARD_GOOGLE_SARIEN
81 config MAINBOARD_PART_NUMBER
82         default "Arcada" if BOARD_GOOGLE_ARCADA
83         default "Sarien" if BOARD_GOOGLE_SARIEN
85 config MAX_CPUS
86         int
87         default 8
89 config UART_FOR_CONSOLE
90         int
91         default 2
93 config VARIANT_DIR
94         default "arcada" if BOARD_GOOGLE_ARCADA
95         default "sarien" if BOARD_GOOGLE_SARIEN
97 config DEVICETREE
98         default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
100 config VBOOT
101         select HAS_RECOVERY_MRC_CACHE
102         select VBOOT_LID_SWITCH
104 # Override the default variant behavior, since the data.vbt is the same
105 # for all variants.
106 config INTEL_GMA_VBT_FILE
107         default "src/mainboard/\$(MAINBOARDDIR)/data.vbt"
109 endif # BOARD_GOOGLE_BASEBOARD_SARIEN