1 ## SPDX-License-Identifier: GPL-2.0-only
3 config BOARD_GOOGLE_VEYRON
8 # Some Veyron boards incorrectly had their RAM code strapped with 100Kohm
9 # resistors. These get overpowered by the SoC's internal pull-downs, so we
10 # cannot read those pins as tri-state. They're restricted to binary RAM codes.
11 config VEYRON_FORCE_BINARY_RAM_CODE
13 default y if BOARD_GOOGLE_VEYRON_JAQ
14 default y if BOARD_GOOGLE_VEYRON_JERRY
15 default y if BOARD_GOOGLE_VEYRON_MIGHTY
18 config BOARD_SPECIFIC_OPTIONS
20 select COMMON_CBFS_SPI_WRAPPER
21 select EC_GOOGLE_CHROMEEC
22 select EC_GOOGLE_CHROMEEC_SPI
23 select SOC_ROCKCHIP_RK3288
24 select MAINBOARD_HAS_CHROMEOS
25 select BOARD_ROMSIZE_KB_4096
27 select SPI_FLASH_GIGADEVICE
28 select SPI_FLASH_WINBOND
30 select MAINBOARD_HAS_TPM1
33 select VBOOT_VBNV_FLASH
36 default "google/veyron"
38 config MAINBOARD_PART_NUMBER
39 default "Veyron_Jaq" if BOARD_GOOGLE_VEYRON_JAQ
40 default "Veyron_Jerry" if BOARD_GOOGLE_VEYRON_JERRY
41 default "Veyron_Mighty" if BOARD_GOOGLE_VEYRON_MIGHTY
42 default "Veyron_Minnie" if BOARD_GOOGLE_VEYRON_MINNIE
43 default "Veyron_Speedy" if BOARD_GOOGLE_VEYRON_SPEEDY
46 config EC_GOOGLE_CHROMEEC_SPI_BUS
50 config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
54 config BOOT_DEVICE_SPI_FLASH_BUS
58 config DRIVER_TPM_I2C_BUS
62 config DRIVER_TPM_I2C_ADDR
66 config CONSOLE_SERIAL_UART_ADDRESS
68 depends on DRIVERS_UART
76 default 0x100000 if CHROMEOS
79 endif # BOARD_GOOGLE_VEYRON