src/mainboard/google/zork/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <string.h>
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <device/mmio.h>
   7 #include <acpi/acpi.h>
   8 #include <acpi/acpigen.h>
   9 #include <amdblocks/amd_pci_util.h>
  10 #include <amdblocks/gpio.h>
  11 #include <amdblocks/smi.h>
  12 #include <baseboard/variants.h>
  13 #include <boardid.h>
  14 #include <gpio.h>
  15 #include <smbios.h>
  16 #include <soc/cpu.h>
  17 #include <soc/gpio.h>
  18 #include <soc/pci_devs.h>
  19 #include <soc/platform_descriptors.h>
  20 #include <soc/southbridge.h>
  21 #include <soc/smi.h>
  22 #include <soc/soc_util.h>
  23 #include <amdblocks/acpimmio.h>
  24 #include <variant/ec.h>
  25 #include <variant/thermal.h>
  26 #include <commonlib/helpers.h>
  27
  28 #define METHOD_BACKLIGHT_ENABLE    "\\_SB.BKEN"
  29 #define METHOD_BACKLIGHT_DISABLE   "\\_SB.BKDS"
  30 #define METHOD_MAINBOARD_INI       "\\_SB.MINI"
  31 #define METHOD_MAINBOARD_WAK       "\\_SB.MWAK"
  32 #define METHOD_MAINBOARD_PTS       "\\_SB.MPTS"
  33
  34 /***********************************************************
  35  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  36  * This table is responsible for physically routing the PIC and
  37  * IOAPIC IRQs to the different PCI devices on the system.  It
  38  * is read and written via registers 0xC00/0xC01 as an
  39  * Index/Data pair.  These values are chipset and mainboard
  40  * dependent and should be updated accordingly.
  41  */
  42 static uint8_t fch_pic_routing[0x80];
  43 static uint8_t fch_apic_routing[0x80];
  44
  45 _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
  46         "PIC and APIC FCH interrupt tables must be the same size");
  47
  48 /*
  49  * This controls the device -> IRQ routing.
  50  *
  51  * Hardcoded IRQs:
  52  *  0: timer < soc/amd/common/acpi/lpc.asl
  53  *  1: i8042 <- ec/google/chromeec/acpi/superio.asl
  54  *  2: cascade
  55  *  8: rtc0 <- soc/amd/common/acpi/lpc.asl
  56  *  9: acpi <- soc/amd/common/acpi/lpc.asl
  57  * 12: i8042 <- ec/google/chromeec/acpi/superio.asl
  58  */
  59 static const struct fch_irq_routing {
  60         uint8_t intr_index;
  61         uint8_t pic_irq_num;
  62         uint8_t apic_irq_num;
  63 } fch_pirq[] = {
  64         { PIRQ_A,       6,              PIRQ_NC },
  65         { PIRQ_B,       13,             PIRQ_NC },
  66         { PIRQ_C,       14,             PIRQ_NC },
  67         { PIRQ_D,       15,             PIRQ_NC },
  68         { PIRQ_E,       15,             PIRQ_NC },
  69         { PIRQ_F,       14,             PIRQ_NC },
  70         { PIRQ_G,       13,             PIRQ_NC },
  71         { PIRQ_H,       6,              PIRQ_NC },
  72
  73         { PIRQ_SCI,     9,              9 },
  74         { PIRQ_EMMC,    5,              5 },
  75         { PIRQ_GPIO,    7,              7 },
  76         { PIRQ_I2C2,    10,             10 },
  77         { PIRQ_I2C3,    11,             11 },
  78         { PIRQ_UART0,   4,              4 },
  79         { PIRQ_UART1,   3,              3 },
  80
  81         /* The MISC registers are not interrupt numbers */
  82         { PIRQ_MISC,    0xfa,           0x00 },
  83         { PIRQ_MISC0,   0x91,           0x00 },
  84         { PIRQ_MISC1,   0x00,           0x00 },
  85         { PIRQ_MISC2,   0x00,           0x00 },
  86 };
  87
  88 static void init_tables(void)
  89 {
  90         const struct fch_irq_routing *entry;
  91         int i;
  92
  93         memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
  94         memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
  95
  96         for (i = 0; i < ARRAY_SIZE(fch_pirq); i++) {
  97                 entry = fch_pirq + i;
  98                 fch_pic_routing[entry->intr_index] = entry->pic_irq_num;
  99                 fch_apic_routing[entry->intr_index] = entry->apic_irq_num;
 100         }
 101 }
 102
 103 /* PIRQ Setup */
 104 static void pirq_setup(void)
 105 {
 106         intr_data_ptr = fch_apic_routing;
 107         picr_data_ptr = fch_pic_routing;
 108 }
 109
 110 static void mainboard_configure_gpios(void)
 111 {
 112         size_t base_num_gpios, override_num_gpios;
 113         const struct soc_amd_gpio *base_gpios, *override_gpios;
 114
 115         base_gpios = baseboard_gpio_table(&base_num_gpios);
 116         override_gpios = variant_override_gpio_table(&override_num_gpios);
 117
 118         gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios,
 119                                           override_num_gpios);
 120 }
 121
 122 static void mainboard_devtree_update(void)
 123 {
 124         variant_audio_update();
 125         variant_bluetooth_update();
 126         variant_touchscreen_update();
 127         variant_devtree_update();
 128 }
 129
 130 static void mainboard_init(void *chip_info)
 131 {
 132         int boardid;
 133
 134         mainboard_ec_init();
 135         boardid = board_id();
 136         printk(BIOS_INFO, "Board ID: %d\n", boardid);
 137
 138         mainboard_configure_gpios();
 139
 140         /* Update DUT configuration */
 141         mainboard_devtree_update();
 142 }
 143
 144 void mainboard_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs,
 145                                         size_t *dxio_num,
 146                                         const fsp_ddi_descriptor **ddi_descs,
 147                                         size_t *ddi_num)
 148 {
 149         variant_get_dxio_ddi_descriptors(dxio_descs, dxio_num, ddi_descs, ddi_num);
 150 }
 151
 152 static void mainboard_write_blken(void)
 153 {
 154         acpigen_write_method(METHOD_BACKLIGHT_ENABLE, 0);
 155         acpigen_soc_clear_tx_gpio(GPIO_85);
 156         acpigen_pop_len();
 157 }
 158
 159 static void mainboard_write_blkdis(void)
 160 {
 161         acpigen_write_method(METHOD_BACKLIGHT_DISABLE, 0);
 162         acpigen_soc_set_tx_gpio(GPIO_85);
 163         acpigen_pop_len();
 164 }
 165
 166 static void mainboard_write_mini(void)
 167 {
 168         acpigen_write_method(METHOD_MAINBOARD_INI, 0);
 169         acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE);
 170         acpigen_pop_len();
 171 }
 172
 173 static void mainboard_write_mwak(void)
 174 {
 175         acpigen_write_method(METHOD_MAINBOARD_WAK, 0);
 176         acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE);
 177         acpigen_pop_len();
 178 }
 179
 180 static void mainboard_write_mpts(void)
 181 {
 182         acpigen_write_method(METHOD_MAINBOARD_PTS, 0);
 183         acpigen_emit_namestring(METHOD_BACKLIGHT_DISABLE);
 184         acpigen_pop_len();
 185 }
 186
 187 static void mainboard_fill_ssdt(const struct device *dev)
 188 {
 189         mainboard_write_blken();
 190         mainboard_write_blkdis();
 191         mainboard_write_mini();
 192         mainboard_write_mpts();
 193         mainboard_write_mwak();
 194 }
 195
 196 /*************************************************
 197  * Dedicated mainboard function
 198  *************************************************/
 199 static void mainboard_enable(struct device *dev)
 200 {
 201         init_tables();
 202         /* Initialize the PIRQ data structures for consumption */
 203         pirq_setup();
 204
 205         dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 206
 207 }
 208
 209 static void mainboard_final(void *chip_info)
 210 {
 211         finalize_gpios(acpi_get_sleep_type());
 212 }
 213
 214 struct chip_operations mainboard_ops = {
 215         .init = mainboard_init,
 216         .enable_dev = mainboard_enable,
 217         .final = mainboard_final,
 218 };
 219
 220 void __weak variant_devtree_update(void)
 221 {
 222 }
 223
 224 __weak const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 225 {
 226         /* Default weak implementation - No overrides. */
 227         *size = 0;
 228         return NULL;
 229 }