src/mainboard/hp/abm/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4
   5 #include <southbridge/amd/common/amd_pci_util.h>
   6 #include <southbridge/amd/agesa/hudson/pci_devs.h>
   7 #include <northbridge/amd/agesa/family16kb/pci_devs.h>
   8
   9 #if 0
  10 static const u8 mainboard_picr_data[0x54] = {
  11         0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
  12         0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  13         0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  14         0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  15         0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  16         0x03, 0x04, 0x05, 0x07
  17 };
  18 static const u8 mainboard_intr_data[0x54] = {
  19         0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
  20         0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  21         0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  22         0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  23         0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  24         0x10, 0x11, 0x12, 0x13
  25 };
  26 #endif
  27
  28 /***********************************************************
  29  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  30  * This table is responsible for physically routing the PIC and
  31  * IOAPIC IRQs to the different PCI devices on the system.  It
  32  * is read and written via registers 0xC00/0xC01 as an
  33  * Index/Data pair.  These values are chipset and mainboard
  34  * dependent and should be updated accordingly.
  35  *
  36  * These values are used by the PCI configuration space,
  37  * MP Tables.  TODO: Make ACPI use these values too.
  38  */
  39 static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
  40         [0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B,  /* INTA# - INTH# */
  41         [0x08] = 0x00, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
  42         [0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F, 0x0A,  /* SCI,  SMBUS0,  ASF,  HDA,  FC,  GEC,  PerfMon,  SD */
  43         [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,            /* IMC INT0 - 5 */
  44         [0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A,       /* USB Devs 18/19/20/22 INTA-C */
  45         [0x40] = 0x0B, 0x0B,                                /* IDE,  SATA */
  46 };
  47
  48 static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
  49         [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,  /* INTA# - INTH# */
  50         [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
  51         [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x10,  /* SCI,  SMBUS0,  ASF,  HDA,  FC,  GEC,  PerMon,  SD */
  52         [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,            /* IMC INT0 - 5 */
  53         [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12,       /* USB Devs 18/19/22/20 INTA-C */
  54         [0x40] = 0x11, 0x13,                                /* IDE,  SATA */
  55 };
  56
  57 /*
  58  * This table defines the index into the picr/intr_data
  59  * tables for each device.  Any enabled device and slot
  60  * that uses hardware interrupts should have an entry
  61  * in this table to define its index into the FCH
  62  * PCI_INTR register 0xC00/0xC01.  This index will define
  63  * the interrupt that it should use.  Putting PIRQ_A into
  64  * the PIN A index for a device will tell that device to
  65  * use PIC IRQ 10 if it uses PIN A for its hardware INT.
  66  */
  67 static const struct pirq_struct mainboard_pirq_data[] = {
  68         /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
  69         {GFX_DEVFN,           {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}},      /* VGA:     01.0 */
  70         {NB_PCIE_PORT2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:     02.2 */
  71         {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:     02.3 */
  72         {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:     02.4 */
  73         {NB_PCIE_PORT5_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:     02.5 */
  74         {SATA_DEVFN,          {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},  /* SATA:    11.0 */
  75         {OHCI1_DEVFN,         {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1:   12.0 */
  76         {EHCI1_DEVFN,         {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1:   12.2 */
  77         {OHCI2_DEVFN,         {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2:   13.0 */
  78         {EHCI2_DEVFN,         {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2:   13.2 */
  79         {SMBUS_DEVFN,         {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS:   14.0 */
  80         {HDA_DEVFN,           {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},   /* HDA:     14.2 */
  81         {SB_PCI_PORT_DEVFN,   {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}},        /* PCIB:    14.4 */
  82         {SD_DEVFN,            {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}},    /* SD:      14.7 */
  83         {OHCI3_DEVFN,         {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3:   16.0 */
  84         {EHCI3_DEVFN,         {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3:   16.2 */
  85 };
  86
  87 /* PIRQ Setup */
  88 static void pirq_setup(void)
  89 {
  90         pirq_data_ptr = mainboard_pirq_data;
  91         pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
  92         intr_data_ptr = mainboard_intr_data;
  93         picr_data_ptr = mainboard_picr_data;
  94 }
  95
  96 /**********************************************
  97  * Enable the dedicated functions of the board.
  98  **********************************************/
  99 static void mainboard_enable(struct device *dev)
 100 {
 101         /* Initialize the PIRQ data structures for consumption */
 102         pirq_setup();
 103 }
 104
 105 struct chip_operations mainboard_ops = {
 106         .enable_dev = mainboard_enable,
 107 };