src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <Porting.h>
   4 #include <AGESA.h>
   5
   6 #include <northbridge/amd/agesa/state_machine.h>
   7 #include <PlatformMemoryConfiguration.h>
   8
   9
  10 /*
  11  * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
  12  *
  13  * Lane Id
  14  * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
  15  * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
  16  * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
  17  * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
  18  * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
  19  * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
  20  * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
  21  * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
  22  * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
  23  * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
  24  * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
  25  * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
  26  * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
  27  * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
  28  * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
  29  * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
  30  * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
  31  * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
  32  * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
  33  * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
  34  * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
  35  * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
  36  * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
  37  * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
  38  * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
  39  * 25 DP0_TX[P,N]1
  40  * 26 DP0_TX[P,N]2
  41  * 27 DP0_TX[P,N]3
  42  * 28 DP1_TX[P,N]0
  43  * 29 DP1_TX[P,N]1
  44  * 30 DP1_TX[P,N]2
  45  * 31 DP1_TX[P,N]3
  46  * 32 DP2_TX[P,N]0
  47  * 33 DP2_TX[P,N]1
  48  * 34 DP2_TX[P,N]2
  49  * 35 DP2_TX[P,N]3
  50  * 36 DP2_TX[P,N]4
  51  * 37 DP2_TX[P,N]5
  52  * 38 DP2_TX[P,N]6
  53  */
  54
  55 static const PCIe_PORT_DESCRIPTOR PortList[] = {
  56         /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */
  57         {
  58                 0,
  59                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
  60                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
  61                                 HotplugDisabled,
  62                                 PcieGenMaxSupported,
  63                                 PcieGenMaxSupported,
  64                                 AspmDisabled, 1)
  65         },
  66         /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
  67         {
  68                 0,
  69                 PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
  70                 PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3,
  71                                 HotplugDisabled,
  72                                 PcieGenMaxSupported,
  73                                 PcieGenMaxSupported,
  74                                 AspmDisabled, 1)
  75         },
  76
  77         /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
  78         {
  79                 0,
  80                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
  81                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
  82                                 HotplugDisabled,
  83                                 PcieGenMaxSupported,
  84                                 PcieGenMaxSupported,
  85                                 AspmDisabled, 1)
  86         },
  87
  88         /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
  89         {
  90                 0,
  91                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
  92                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
  93                                 HotplugDisabled,
  94                                 PcieGenMaxSupported,
  95                                 PcieGenMaxSupported,
  96                                 AspmDisabled, 1)
  97         },
  98
  99         /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
 100         {
 101                 0,
 102                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
 103                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
 104                                 HotplugDisabled,
 105                                 PcieGenMaxSupported,
 106                                 PcieGenMaxSupported,
 107                                 AspmDisabled, 1)
 108         },
 109
 110         /* PCIe port, Lanes 7, PCI Device Number 7, LAN */
 111         {
 112                 0,
 113                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
 114                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
 115                                 HotplugDisabled,
 116                                 PcieGenMaxSupported,
 117                                 PcieGenMaxSupported,
 118                                 AspmDisabled, 1)
 119         },
 120
 121         /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
 122         {
 123                 DESCRIPTOR_TERMINATE_LIST,
 124                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
 125                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
 126                                 HotplugDisabled,
 127                                 PcieGenMaxSupported,
 128                                 PcieGenMaxSupported,
 129                                 AspmDisabled, 0)
 130         },
 131 };
 132
 133 static const PCIe_DDI_DESCRIPTOR DdiList[] = {
 134         /* DP0 to HDMI0/DP */
 135         {
 136                 0,
 137                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
 138                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
 139         },
 140         /* DP1 to FCH */
 141         {
 142                 0,
 143                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
 144                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
 145         },
 146         /* DP2 to HDMI1/DP */
 147         {
 148                 DESCRIPTOR_TERMINATE_LIST,
 149                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
 150                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
 151         },
 152 };
 153
 154 void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 155 {
 156         FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
 157         FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
 158         FchReset->Xhci1Enable = FALSE;
 159 }
 160
 161 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 162         .Flags        = DESCRIPTOR_TERMINATE_LIST,
 163         .SocketId     = 0,
 164         .PciePortList = PortList,
 165         .DdiLinkList  = DdiList,
 166 };
 167
 168 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 169 {
 170         InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 171 }
 172
 173 /*----------------------------------------------------------------------------------------
 174  *                        CUSTOMER OVERRIDES MEMORY TABLE
 175  *----------------------------------------------------------------------------------------
 176  */
 177
 178 /*
 179  * Platform Specific Overriding Table allows IBV/OEM to pass in platform
 180  * information to AGESA
 181  * (e.g. MemClk routing, the number of DIMM slots per channel,...).
 182  * If PlatformSpecificTable is populated, AGESA will base its settings on the
 183  * data from the table. Otherwise, it will use its default conservative settings
 184  */
 185 static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
 186         NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
 187         NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
 188         MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
 189         CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
 190         ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
 191         CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
 192
 193         PSO_END
 194 };
 195
 196 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 197 {
 198         InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
 199 }
 200
 201 void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
 202 {
 203         /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
 204         InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
 205 }