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payloads/edk2: Disable the CPU Timer Lib unless supported
[coreboot.git] / src / mainboard / intel / adlrvp / devicetree_m.cb
blob9a5937e65ef0f797fec1638028410f510a36d408
1 fw_config
2 field AUDIO 8 10
3 option NONE 0
4 option ADL_MAX98373_ALC5682I_I2S 1
5 end
6 end
7 chip soc/intel/alderlake
8
9 device cpu_cluster 0 on
10 device lapic 0 on end
11 end
12
13 # GPE configuration
14 # Note that GPE events called out in ASL code rely on this
15 # route. i.e. If this route changes then the affected GPE
16 # offset bits also need to be changed.
17 register "pmc_gpe0_dw0" = "GPP_B"
18 register "pmc_gpe0_dw1" = "GPP_D"
19 register "pmc_gpe0_dw2" = "GPP_E"
20
21 # FSP configuration
22 register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0
23 register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1
24 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
25 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
26 register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A port 1
27 register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # Type-A port 2
28 register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
29 register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
30 register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3
31 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
32
33 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 1
34 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 2
35 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
36 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WLAN
37
38 # Sagv Configuration
39 register "sagv" = "SaGv_Enabled"
40
41 # Enable CNVi Bluetooth
42 register "cnvi_bt_core" = "true"
43
44 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
45 register "gen1_dec" = "0x00fc0801"
46 register "gen2_dec" = "0x000c0201"
47 # EC memory map range is 0x900-0x9ff
48 register "gen3_dec" = "0x00fc0901"
49
50 #Enable PCH PCIE RP 4 using CLK 5
51 register "pch_pcie_rp[PCH_RP(4)]" = "{
52 .clk_src = 5,
53 .clk_req = 5,
54 .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
55 .PcieRpL1Substates = L1_SS_L1_2,
56 }"
57
58 # Enable PCH PCIE RP 5 using CLK 2
59 register "pch_pcie_rp[PCH_RP(5)]" = "{
60 .clk_src = 2,
61 .clk_req = 2,
62 .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
63 .PcieRpL1Substates = L1_SS_L1_2,
64 }"
65
66 # Enable PCH PCIE RP 9 using CLK 3
67 register "pch_pcie_rp[PCH_RP(9)]" = "{
68 .clk_src = 3,
69 .clk_req = 3,
70 .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
71 .PcieRpL1Substates = L1_SS_L1_2,
72 }"
73
74 #Enable PCH PCIE RP 10 using CLK 1
75 register "pch_pcie_rp[PCH_RP(10)]" = "{
76 .clk_src = 1,
77 .clk_req = 1,
78 .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
79 .PcieRpL1Substates = L1_SS_L1_2,
80 }"
81
82 # Hybrid storage mode
83 register "hybrid_storage_mode" = "1"
84
85 # Enable CPU PCIE RP 1 using CLK 0
86 register "cpu_pcie_rp[CPU_RP(1)]" = "{
87 .clk_req = 0,
88 .clk_src = 0,
89 .flags = PCIE_RP_LTR | PCIE_RP_AER,
90 }"
91
92 # Enable EDP in PortA
93 register "ddi_portA_config" = "1"
94 # Enable HDMI in Port B
95 register "ddi_ports_config" = "{
96 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
97 }"
98
99 # TCSS USB3
100 register "tcss_aux_ori" = "0"
101
102 register "s0ix_enable" = "1"
103
104 register "serial_io_i2c_mode" = "{
105 [PchSerialIoIndexI2C0] = PchSerialIoPci,
106 [PchSerialIoIndexI2C1] = PchSerialIoPci,
107 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
108 [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
109 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
110 [PchSerialIoIndexI2C5] = PchSerialIoPci,
111 }"
112
113 register "serial_io_gspi_mode" = "{
114 [PchSerialIoIndexGSPI0] = PchSerialIoPci,
115 [PchSerialIoIndexGSPI1] = PchSerialIoPci,
116 [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
117 [PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
118 }"
119
120 register "serial_io_gspi_cs_mode" = "{
121 [PchSerialIoIndexGSPI0] = 0,
122 [PchSerialIoIndexGSPI1] = 1,
123 [PchSerialIoIndexGSPI2] = 0,
124 [PchSerialIoIndexGSPI3] = 0,
125 }"
126
127 register "serial_io_gspi_cs_state" = "{
128 [PchSerialIoIndexGSPI0] = 0,
129 [PchSerialIoIndexGSPI1] = 0,
130 [PchSerialIoIndexGSPI2] = 0,
131 [PchSerialIoIndexGSPI3] = 0,
132 }"
133
134 register "serial_io_uart_mode" = "{
135 [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
136 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
137 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
138 }"
139
140 # HD Audio
141 register "pch_hda_dsp_enable" = "1"
142 register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
143 register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
144 register "pch_hda_idisp_codec_enable" = "1"
145
146 # Intel Common SoC Config
147 register "common_soc_config" = "{
148 .gspi[1] = {
149 .speed_mhz = 1,
150 .early_init = 1,
151 },
152 .i2c[0] = {
153 .speed = I2C_SPEED_FAST,
154 },
155 .i2c[1] = {
156 .speed = I2C_SPEED_FAST,
157 },
158 .i2c[2] = {
159 .speed = I2C_SPEED_FAST,
160 },
161 .i2c[3] = {
162 .speed = I2C_SPEED_FAST,
163 },
164 .i2c[5] = {
165 .speed = I2C_SPEED_FAST,
166 },
167 }"
168
169 device domain 0 on
170 device ref pcie5_0 on end
171 device ref igpu on end
172 device ref dtt on end
173 device ref ipu on
174 chip drivers/intel/mipi_camera
175 register "acpi_uid" = "0x50000"
176 register "acpi_name" = ""IPU0""
177 register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
178
179 register "cio2_num_ports" = "2"
180 register "cio2_lanes_used" = "{2,2}"
181 register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
182 register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
183 register "cio2_prt[0]" = "2"
184 register "cio2_prt[1]" = "1"
185 device generic 0 on end
186 end
187 end
188 device ref pcie4_0 on end
189 device ref pcie4_1 on end
190 device ref tbt_pcie_rp0 on end
191 device ref tbt_pcie_rp1 on end
192 device ref tcss_xhci on
193 chip drivers/usb/acpi
194 register "type" = "UPC_TYPE_HUB"
195 device ref tcss_root_hub on
196 chip drivers/usb/acpi
197 register "desc" = ""TypeC Port 1""
198 device ref tcss_usb3_port1 on end
199 end
200 chip drivers/usb/acpi
201 register "desc" = ""TypeC Port 2""
202 device ref tcss_usb3_port2 on end
203 end
204 end
205 end
206 end
207 device ref tcss_dma0 on end
208 device ref xhci on
209 chip drivers/usb/acpi
210 register "desc" = ""Root Hub""
211 register "type" = "UPC_TYPE_HUB"
212 device ref xhci_root_hub on
213 chip drivers/usb/acpi
214 register "desc" = ""Bluetooth""
215 register "type" = "UPC_TYPE_INTERNAL"
216 device ref usb2_port10 on end
217 end
218 end
219 end
220 end
221 device ref cnvi_wifi on
222 chip drivers/wifi/generic
223 register "wake" = "GPE0_PME_B0"
224 device generic 0 on end
225 end
226 end
227 device ref i2c0 on
228 chip drivers/i2c/generic
229 register "hid" = ""10EC5682""
230 register "name" = ""RT58""
231 register "desc" = ""Headset Codec""
232 register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_H3_IRQ)"
233 # Set the jd_src to RT5668_JD1 for jack detection
234 register "property_count" = "1"
235 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
236 register "property_list[0].name" = ""realtek,jd-src""
237 register "property_list[0].integer" = "1"
238 device i2c 1a on
239 probe AUDIO ADL_MAX98373_ALC5682I_I2S
240 end
241 end
242 chip drivers/i2c/max98373
243 register "vmon_slot_no" = "0"
244 register "imon_slot_no" = "1"
245 register "uid" = "0"
246 register "desc" = ""Right Speaker Amp""
247 register "name" = ""MAXR""
248 device i2c 31 on
249 probe AUDIO ADL_MAX98373_ALC5682I_I2S
250 end
251 end
252 chip drivers/i2c/max98373
253 register "vmon_slot_no" = "2"
254 register "imon_slot_no" = "3"
255 register "uid" = "1"
256 register "desc" = ""Left Speaker Amp""
257 register "name" = ""MAXL""
258 device i2c 32 on
259 probe AUDIO ADL_MAX98373_ALC5682I_I2S
260 end
261 end
262 chip drivers/i2c/hid
263 register "generic.hid" = ""WACOM PWB-D893""
264 register "generic.desc" = ""WACOM Touchscreen""
265 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
266 register "generic.probed" = "1"
267 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)"
268 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)"
269 register "generic.enable_delay_ms" = "1"
270 register "generic.reset_delay_ms" = "300"
271 register "generic.has_power_resource" = "1"
272 register "generic.disable_gpio_export_in_crs" = "1"
273 register "hid_desc_reg_offset" = "0x01"
274 device i2c 0a on end
275 end
276 chip drivers/i2c/hid
277 register "generic.hid" = ""ELAN0000""
278 register "generic.desc" = ""ELAN Touchpad""
279 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D11_IRQ)"
280 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H1)"
281 register "generic.wake" = "GPE0_DW1_11"
282 register "generic.detect" = "1"
283 register "generic.has_power_resource" = "1"
284 device i2c 15 on end
285 end
286 end
287 device ref i2c1 on
288 chip drivers/intel/mipi_camera
289 register "acpi_hid" = ""OVTI5675""
290 register "acpi_uid" = "0"
291 register "acpi_name" = ""CAM0""
292 register "chip_name" = ""Ov 5675 Camera""
293 register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
294
295 register "ssdb.lanes_used" = "2"
296 register "ssdb.vcm_type" = "0x0C"
297 register "vcm_name" = ""VCM0""
298 register "num_freq_entries" = "1"
299 register "link_freq[0]" = "450000000"
300 register "remote_name" = ""IPU0""
301
302 register "has_power_resource" = "1"
303 #Controls
304 register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
305 register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
306 register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
307 register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
308
309 #_ON
310 register "on_seq.ops_cnt" = "4"
311 register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
312 register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
313 register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
314 register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
315
316 #_OFF
317 register "off_seq.ops_cnt" = "3"
318 register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
319 register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
320 register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
321
322 device i2c 36 on end
323 end
324 chip drivers/intel/mipi_camera
325 register "acpi_uid" = "3"
326 register "acpi_name" = ""VCM0""
327 register "chip_name" = ""DW AF VCM""
328 register "device_type" = "INTEL_ACPI_CAMERA_VCM"
329
330 register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
331 register "vcm_compat" = ""dongwoon,dw9714""
332
333 device i2c 0C on end
334 end
335 end
336 device ref i2c2 on end
337 device ref i2c3 on end
338 device ref heci1 on end
339 device ref sata on end
340 device ref i2c5 on
341 chip drivers/intel/mipi_camera
342 register "acpi_hid" = ""OVTI5675""
343 register "acpi_uid" = "0"
344 register "acpi_name" = ""CAM1""
345 register "chip_name" = ""Ov 5675 Camera""
346 register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
347
348 register "ssdb.lanes_used" = "2"
349 register "num_freq_entries" = "1"
350 register "link_freq[0]" = "450000000"
351 register "remote_name" = ""IPU0""
352
353 register "has_power_resource" = "1"
354 #Controls
355 register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
356 register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
357 register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
358 register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
359
360 #_ON
361 register "on_seq.ops_cnt" = "4"
362 register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
363 register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
364 register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
365 register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
366
367 #_OFF
368 register "off_seq.ops_cnt" = "3"
369 register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
370 register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
371 register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
372
373 device i2c 36 on end
374 end
375 end
376 device ref pcie_rp1 on end
377 device ref pcie_rp3 on end # W/A to FSP issue
378 device ref pcie_rp4 on end # W/A to FSP issue
379 device ref pcie_rp5 on end
380 device ref pcie_rp6 on end
381 device ref pcie_rp8 on end
382 device ref pcie_rp9 on end
383 device ref pcie_rp10 on end
384 device ref uart0 on end
385 device ref gspi0 on end
386 device ref p2sb on end
387 device pci 1e.3 on
388 chip drivers/spi/acpi
389 register "hid" = "ACPI_DT_NAMESPACE_HID"
390 register "compat_string" = ""google,cr50""
391 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)"
392 device spi 0 on end
393 end
394 end # GSPI1
395 device ref hda on
396 chip drivers/intel/soundwire
397 device generic 0 on
398 chip drivers/soundwire/alc711
399 # SoundWire Link 0 ID 1
400 register "desc" = ""Headset Codec""
401 device generic 0.1 on end
402 end
403 end
404 end
405 end
406 device ref smbus on end
407 end
408 end
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