src/mainboard/intel/adlrvp/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <types.h>
   6 #include <vendorcode/google/chromeos/chromeos.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config gpio_table[] = {
  10
  11         /* GPIO A0-A6, A9-A10 default function is NF1 for eSPI interface when
  12           eSPI is enabled */
  13
  14         /* SSD1_PWREN  CPU SSD1 */
  15         PAD_CFG_GPO(GPP_D14, 1, PLTRST),
  16         /* SSD1_RESET  CPU SSD1 */
  17         PAD_CFG_GPO(GPP_F20, 1, PLTRST),
  18         /* BT_RF_KILL_N */
  19         PAD_CFG_GPO(GPP_A13, 1, PLTRST),
  20         /* WLAN RST# */
  21         PAD_CFG_GPO(GPP_H2, 1, PLTRST),
  22         /* WIFI_WAKE_N */
  23         PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT),
  24         /* x4 PCIE slot1 PWREN */
  25         PAD_CFG_GPO(GPP_H17, 0, PLTRST),
  26         /* x4 PCIE slot 1 RESET */
  27         PAD_CFG_GPO(GPP_F10, 1, PLTRST),
  28         /* Retimer Force Power */
  29         PAD_CFG_GPO(GPP_E4, 0, PLTRST),
  30         /* PEG Slot RST# */
  31         PAD_CFG_GPO(GPP_B2, 1, PLTRST),
  32         /* M.2 SSD_2 Reset */
  33         PAD_CFG_GPO(GPP_H0, 1, PLTRST),
  34         /* CAM_STROBE */
  35         PAD_CFG_GPO(GPP_B18, 0, PLTRST),
  36         /* Audio Codec INT N */
  37         PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT),
  38         /* TCH PAD Power EN */
  39         PAD_CFG_GPO(GPP_F7, 1, PLTRST),
  40         /* THC1 SPI2 RST# */
  41         PAD_CFG_GPO(GPP_F17, 1, PLTRST),
  42         /* THC1_SPI2_INTB */
  43         PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
  44         /* THC1_SPI2_INTB */
  45         PAD_CFG_GPI(GPP_E17, NONE, PLTRST),
  46         /* EC_SLP_S0_CS_N */
  47         PAD_CFG_GPO(GPP_F9, 1, PLTRST),
  48         /* DISP_AUX_N_BIAS_GPIO */
  49         PAD_CFG_GPO(GPP_E23, 1, PLTRST),
  50         /* WWAN WAKE N*/
  51         PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
  52         /* WWAN_DISABLE_N */
  53         PAD_CFG_GPO(GPP_D15, 1, DEEP),
  54         /* WWAN_RST# */
  55         PAD_CFG_GPO(GPP_F14, 1, DEEP),
  56         /* WWAN_FCP_OFF_N */
  57         PAD_CFG_GPO(GPP_F15, 1, DEEP),
  58         /* WWAN_PWR_EN */
  59         PAD_CFG_GPO(GPP_F21, 1, DEEP),
  60         /* WWAN_PERST# */
  61         PAD_CFG_GPO(GPP_C5, 1, DEEP),
  62         /* PEG_SLOT_WAKE_N */
  63         PAD_CFG_GPI(GPP_A20, NONE, PLTRST),
  64         /* CAM CONN1 CLKEN */
  65         PAD_CFG_GPO(GPP_H15, 1, PLTRST),
  66         /* CPU SSD2 PWREN */
  67         PAD_CFG_GPO(GPP_C2, 1, PLTRST),
  68         /* CPU SSD2 RST# */
  69         PAD_CFG_GPO(GPP_H1, 1, PLTRST),
  70         /* Sata direct Power */
  71         PAD_CFG_GPO(GPP_B4, 1, PLTRST),
  72         /* M.2_PCH_SSD_PWREN */
  73         PAD_CFG_GPO(GPP_D16, 1, PLTRST),
  74
  75         /* CAM1_RST */
  76         PAD_CFG_GPO(GPP_R5, 1, PLTRST),
  77         /* CAM2_RST */
  78         PAD_CFG_GPO(GPP_E15, 1, PLTRST),
  79         /* CAM1_PWR_EN */
  80         PAD_CFG_GPO(GPP_B23, 1, PLTRST),
  81         /* CAM2_PWR_EN */
  82         PAD_CFG_GPO(GPP_E16, 1, PLTRST),
  83         /* M.2_SSD_PDET_R */
  84         PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
  85         /* THC0 SPI1 CLK */
  86         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2),
  87         /* THC0 SPI1 IO 1 */
  88         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2),
  89         /* THC0 SPI1 IO 2 */
  90         PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2),
  91         /* THC0 SPI IO 3 */
  92         PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2),
  93         /* THC1 SPI1 RSTB */
  94         PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2),
  95         /* UART_RX(1) */
  96         PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
  97         /* UART_RX(2) */
  98         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
  99         /* UART_RX(4) */
 100         PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),
 101         /* UART_RX(5) */
 102         PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1),
 103         /* UART_RX(6) */
 104         PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1),
 105
 106         /* UART_TX(1) */
 107         PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
 108         /* UART_TX(2) */
 109         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 110         /* UART_TX(4) */
 111         PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1),
 112         /* UART_TX(5) */
 113         PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1),
 114         /* UART_TX(6) */
 115         PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1),
 116
 117         /* UART_RTS(1) */
 118         PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
 119         /* UART_RTS(2) */
 120         PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
 121         /* UART_RTS(4) */
 122         PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),
 123         /* UART_RTS(5) */
 124         PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1),
 125         /* UART_RTS(6) */
 126         PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1),
 127
 128         /* UART_CTS(1) */
 129         PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
 130         /* UART_CTS(2) */
 131         PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
 132         /* UART_CTS(4) */
 133         PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),
 134         /* UART_CTS(5) */
 135         PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1),
 136         /* UART_CTS(6) */
 137         PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1),
 138
 139         /* SPI_MOSI(1) */
 140         PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
 141         /* SPI_MOSI(2) */
 142         PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
 143
 144         /* SPI_MIS0(1) */
 145         PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
 146         /* SPI_MIS0(2) */
 147         PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
 148
 149         /* SPI_CLK(1) */
 150         PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
 151         /* SPI_CLK(2) */
 152         PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
 153
 154         /* SPI_CS(0, 1) */
 155         PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
 156         /* SPI_CS(1, 0) */
 157         PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
 158         /* SPI_CS(2, 0) */
 159         PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2),
 160
 161         /* I2C_SCL(0) */
 162         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 163         /* I2C_SCL(1) */
 164         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 165         /* I2C_SCL(2) */
 166         PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
 167         /* I2C_SCL(3) */
 168         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
 169         /* I2C_SCL(5) */
 170         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
 171
 172         /* I2C_SDA(0) */
 173         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 174         /* I2C_SDA(1) */
 175         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 176         /* I2C_SDA(2) */
 177         PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
 178         /* I2C_SDA(3) */
 179         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
 180         /* I2C_SDA(5) */
 181         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
 182
 183         /* I2S0_SCLK */
 184         PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
 185         /* I2S0_SFRM */
 186         PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
 187         /* I2S0_TXD */
 188         PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
 189         /* I2S0_RXD */
 190         PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
 191
 192         /* I2S_MCLK1_OUT */
 193         PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 194         /* I2S_MCLK2_INOUT */
 195         PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
 196
 197         /* SNDW1_CLK */
 198         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
 199         /* SNDW1_DATA */
 200         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
 201         /* SNDW2_CLK */
 202         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
 203         /* SNDW2_DATA */
 204         PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
 205         /* SNDW3_CLK */
 206         PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
 207         /* SNDW3_DATA */
 208         PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
 209         /* SNDW4_CLK */
 210         PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
 211         /* SNDW4_DATA */
 212         PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
 213
 214         /* SMB_CLK */
 215         PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
 216         /* SMB_DATA */
 217         PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 218
 219         /* SATA DEVSLP */
 220         PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4),
 221         PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
 222
 223         /* SATA LED pin */
 224         PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
 225
 226         /* USB2 OC0 pins */
 227         PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 228         /* USB2 OC3 pins */
 229         PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
 230
 231         /* GPIO pin for PCIE SRCCLKREQB */
 232         PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 233         PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
 234         PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 235         PAD_NC(GPP_D8, NONE),
 236         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
 237         PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
 238         PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
 239
 240         /* DDP1/2/3/4/A/B/C  CTRLCLK and CTRLDATA pins */
 241         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
 242         PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
 243         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
 244         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
 245         PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2),
 246         PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
 247         PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
 248
 249         /* HPD_1 (E14) and HPD_2 (A18) pins */
 250         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 251         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
 252
 253         /* IMGCLKOUT */
 254         PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
 255         PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
 256         PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
 257         PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 258         /* H23 : CLKREQ5_WWAN_N */
 259         PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
 260
 261         /* A21 : HDMI CRLS CTRLCLK */
 262         PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
 263         /* A22 : HDMI CRLS CTRLDATA */
 264         PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
 265         /* H1_PCH_INT_ODL */
 266         PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT)
 267 };
 268
 269 void variant_configure_gpio_pads(void)
 270 {
 271         gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 272 }
 273
 274 static const struct cros_gpio cros_gpios[] = {
 275         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 276 };
 277 DECLARE_CROS_GPIOS(cros_gpios);