src/mainboard/intel/galileo/gen1.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* PCIe reset pin */
   4 #define GEN1_PCI_RESET_RESUMEWELL_GPIO          3
   5
   6 /* Jumper J2 determines the slave address of Cypress I/O GPIO expander */
   7 #define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO     5
   8
   9 static const struct reg_script gen1_gpio_init[] = {
  10         /* Initialize the legacy GPIO controller */
  11         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03),
  12         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x00),
  13         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00),
  14         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00),
  15         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00),
  16         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00),
  17         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00),
  18         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03),
  19         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00),
  20
  21         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f),
  22         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x21),
  23         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x14),
  24         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00),
  25         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00),
  26         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00),
  27         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00),
  28         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f),
  29         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00),
  30
  31         /* Initialize the GPIO controller */
  32         REG_GPIO_WRITE(GPIO_INTEN, 0),
  33         REG_GPIO_WRITE(GPIO_INTSTATUS, 0),
  34         REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5),
  35         REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 0x15),
  36         REG_GPIO_WRITE(GPIO_INTMASK, 0),
  37         REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0),
  38         REG_GPIO_WRITE(GPIO_INT_POLARITY, 0),
  39         REG_GPIO_WRITE(GPIO_DEBOUNCE, 0),
  40         REG_GPIO_WRITE(GPIO_LS_SYNC, 0),
  41
  42         /* Toggle the Cypress reset line */
  43         REG_GPIO_OR(GPIO_SWPORTA_DR, BIT4),
  44         REG_GPIO_AND(GPIO_SWPORTA_DR, ~BIT4),
  45
  46         REG_SCRIPT_END
  47 };
  48
  49 static const struct reg_script gen1_hsuart0_0x20[] = {
  50         /* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1
  51          * Set IO1_MUX (EXP.PORT3_5) output, low
  52          * Set LVL_OE (GPIO_SUS2) output, high
  53          */
  54
  55         REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3),
  56         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
  57         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT5),
  58
  59         /* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD
  60          * Set IO0_MUX (EXP.PORT3_4) output, low
  61          * Set LVL_OE (GPIO_SUS2) output, high
  62          */
  63         REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3),
  64         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT4),
  65         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT4),
  66
  67         REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2),
  68         REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2),
  69         REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2),
  70
  71         REG_SCRIPT_END
  72 };
  73
  74 static const struct reg_script gen1_hsuart0_0x21[] = {
  75         /* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1
  76          * Set IO1_MUX (EXP.PORT3_5) output, low
  77          * Set LVL_OE (GPIO_SUS2) output, high
  78          */
  79
  80         REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3),
  81         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
  82         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT5),
  83
  84         /* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD
  85          * Set IO0_MUX (EXP.PORT3_4) output, low
  86          * Set LVL_OE (GPIO_SUS2) output, high
  87          */
  88         REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3),
  89         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT4),
  90         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT4),
  91
  92         REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2),
  93         REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2),
  94         REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2),
  95
  96         REG_SCRIPT_END
  97 };
  98
  99 static const struct reg_script gen1_i2c_0x20_init[] = {
 100         /* Route I2C pins to Arduino header:
 101          * Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector
 102          *
 103          *      I2C_SDA -> ANALOG_A4
 104          *      I2C_SCL -> ANALOG_A5
 105          */
 106         REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 1),
 107         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
 108         REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT1, ~BIT5),
 109
 110         /* Set all GPIO expander pins connected to the Reset Button as inputs
 111          * Configure RESET_N_SHLD (GPORT5_BIT0) and SW_RESET_N_SHLD
 112          * (GPORT5_BIT1) as inputs
 113          */
 114         REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 5),
 115         REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, BIT1 | BIT0),
 116
 117         REG_SCRIPT_END
 118 };
 119
 120 static const struct reg_script gen1_i2c_0x21_init[] = {
 121         /* Route I2C pins to Arduino header:
 122          * Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector
 123          *
 124          *      I2C_SDA -> ANALOG_A4
 125          *      I2C_SCL -> ANALOG_A5
 126          */
 127         REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 1),
 128         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
 129         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT1, ~BIT5),
 130
 131         /* Set all GPIO expander pins connected to the Reset Button as inputs
 132          * Configure RESET_N_SHLD (GPORT5_BIT0) and SW_RESET_N_SHLD
 133          * (GPORT5_BIT1) as inputs
 134          */
 135         REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 5),
 136         REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, BIT1 | BIT0),
 137
 138         REG_SCRIPT_END
 139 };
 140
 141 static const struct reg_script gen1_tpm_reset_0x20[] = {
 142         /* Reset the TPM using SW_RESET_N_SHLD (GPORT5_BIT1):
 143          * low, output, delay, input
 144          */
 145         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT5, ~BIT1),
 146         REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 5),
 147         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT1),
 148         TIME_DELAY_USEC(5),
 149         REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, BIT1),
 150
 151         REG_SCRIPT_END
 152 };
 153
 154 static const struct reg_script gen1_tpm_reset_0x21[] = {
 155         /* Reset the TPM using SW_RESET_N_SHLD (GPORT5_BIT1):
 156          * low, output, delay, input
 157          */
 158         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT5, ~BIT1),
 159         REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 5),
 160         REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT1),
 161         TIME_DELAY_USEC(5),
 162         REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, BIT1),
 163
 164         REG_SCRIPT_END
 165 };