src/mainboard/intel/galileo/gen2.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* PCIe reset pin */
   4 #define GEN2_PCI_RESET_RESUMEWELL_GPIO          0
   5
   6 static const struct reg_script gen2_gpio_init[] = {
   7         /* Initialize the legacy GPIO controller */
   8         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03),
   9         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x03),
  10         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00),
  11         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00),
  12         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00),
  13         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00),
  14         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00),
  15         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03),
  16         REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00),
  17
  18         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f),
  19         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x1c),
  20         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x02),
  21         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00),
  22         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00),
  23         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00),
  24         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00),
  25         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f),
  26         REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00),
  27
  28         /* Initialize the GPIO controller */
  29         REG_GPIO_WRITE(GPIO_INTEN, 0),
  30         REG_GPIO_WRITE(GPIO_INTSTATUS, 0),
  31         REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5),
  32         REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 5),
  33         REG_GPIO_WRITE(GPIO_INTMASK, 0),
  34         REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0),
  35         REG_GPIO_WRITE(GPIO_INT_POLARITY, 0),
  36         REG_GPIO_WRITE(GPIO_DEBOUNCE, 0),
  37         REG_GPIO_WRITE(GPIO_LS_SYNC, 0),
  38
  39         REG_SCRIPT_END
  40 };
  41
  42 static const struct reg_script gen2_hsuart0[] = {
  43         /* Route UART0_TXD to MUX7_Y -> BUF_IO1 -> IO1 -> DIGITAL 1
  44          * Set MUX7_SEL (EXP1.P1_5) high
  45          * Configure MUX7_SEL (EXP1.P1_5) as an output
  46          * Set LVL_B_OE6_N (EXP0.P1_4) low
  47          * Configure LVL_B_OE6_N (EXP0.P1_4) as an output
  48          */
  49         REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT1, BIT5),
  50         REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, ~BIT5),
  51         REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_OUTPUT1, ~BIT4),
  52         REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_CONFIG1, ~BIT4),
  53
  54         /* Route DIGITAL 0 -> IO0 -> UART0_RXD
  55          * Set LVL_C_OE0_N (EXP1.P0_0) high
  56          * Configure LVL_C_OE0_N (EXP1.P0_0) as an output
  57          */
  58         REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT0, BIT0),
  59         REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG0, ~BIT0),
  60
  61         REG_SCRIPT_END
  62 };
  63
  64 static const struct reg_script gen2_i2c_init[] = {
  65         /* Route I2C to Arduino Shield connector:
  66          * Set AMUX1_IN (EXP2.P1_4) low
  67          * Configure AMUX1_IN (EXP2.P1_4) as an output
  68          *
  69          *      I2C_SDA -> ANALOG_A4
  70          *      I2C_SCL -> ANALOG_A5
  71          */
  72         REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_OUTPUT1, ~BIT4),
  73         REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_CONFIG1, ~BIT4),
  74
  75         /* Set all GPIO expander pins connected to the Reset Button as inputs
  76          * Configure Reset Button(EXP1.P1_7) as an input
  77          * Disable pullup on Reset Button(EXP1.P1_7)
  78          * Configure Reset Button(EXP2.P1_7) as an input
  79          * Disable pullup on Reset Button(EXP2.P1_7)
  80          */
  81         REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, BIT7),
  82         REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_PULL_UP_DOWN_EN1, ~BIT7),
  83         REG_I2C_OR(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_CONFIG1, BIT7),
  84         REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_PULL_UP_DOWN_EN1, ~BIT7),
  85
  86         REG_SCRIPT_END
  87 };
  88
  89 static const struct reg_script gen2_tpm_reset[] = {
  90         /* Reset the TPM using SW_RESET_N_SHLD (EXP1 P1.7):
  91          * low, output, delay, input
  92          */
  93         REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT1, ~BIT7),
  94         REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, ~BIT7),
  95         TIME_DELAY_USEC(5),
  96         REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, BIT7),
  97
  98         REG_SCRIPT_END
  99 };