src/mainboard/intel/glkrvp/chromeos.fmd

   1 FLASH 16M {
   2         WP_RO@0x0 0x400000 {
   3                 SI_DESC@0x0 0x1000
   4                 IFWI@0x1000 0x1ff000
   5                 RO_VPD(PRESERVE)@0x200000 0x4000
   6                 RO_SECTION@0x204000 0x1fc000 {
   7                         FMAP@0x0 0x800
   8                         RO_FRID@0x800 0x40
   9                         RO_FRID_PAD@0x840 0x7c0
  10                         COREBOOT(CBFS)@0x1000 0x1ab000
  11                         GBB@0x1ac000 0x40000
  12                         RO_UNUSED@0x1ec000 0x10000
  13                 }
  14         }
  15         MISC_RW@0x400000 0x4a000 {
  16                 UNIFIED_MRC_CACHE@0x0 0x31000 {
  17                         RECOVERY_MRC_CACHE@0x0 0x10000
  18                         RW_MRC_CACHE@0x10000 0x20000
  19                         RW_VAR_MRC_CACHE@0x30000 0x1000
  20                 }
  21                 RW_ELOG(PRESERVE)@0x31000 0x4000
  22                 RW_SHARED@0x35000 0x4000 {
  23                         SHARED_DATA@0x0 0x2000
  24                         VBLOCK_DEV@0x2000 0x2000
  25                 }
  26                 RW_VPD(PRESERVE)@0x39000 0x2000
  27                 FPF_STATUS@0x3B000 0x1000
  28                 TMP_UNUSED_HOLE@0x3C000 0xE000
  29         }
  30         RW_SECTION_A@0x44a000 0x477800 {
  31                 VBLOCK_A@0x0 0x10000
  32                 FW_MAIN_A(CBFS)@0x10000 0x4677c0
  33                 RW_FWID_A@0x4777c0 0x40
  34         }
  35         RW_SECTION_B@0x8c1800 0x477800 {
  36                 VBLOCK_B@0x0 0x10000
  37                 FW_MAIN_B(CBFS)@0x10000 0x4677c0
  38                 RW_FWID_B@0x4777c0 0x40
  39         }
  40         RW_NVRAM(PRESERVE)@0xd39000 0x6000
  41         SMMSTORE(PRESERVE)@0xd40000 0x40000
  42         RW_LEGACY(CBFS)@0xd80000 0x1b0000
  43         BIOS_UNUSABLE@0xf3f000 0x40000
  44         DEVICE_EXTENSION@0xf7f000 0x80000
  45         # Currently, it is required that the BIOS region be a multiple of 8KiB.
  46         # This is required so that the recovery mechanism can find SIGN_CSE
  47         # region aligned to 4K at the center of BIOS region. Since the
  48         # descriptor at the beginning uses 4K and BIOS starts at an offset of
  49         # 4K, a hole of 4K is created towards the end of the flash to compensate
  50         # for the size requirement of BIOS region.
  51         # FIT tool thus creates descriptor with following regions:
  52         # Descriptor --> 0 to 4K
  53         # BIOS       --> 4K to 0xf7f000
  54         # Device ext --> 0xf7f000 to 0xfff000
  55         UNUSED_HOLE@0xfff000 0x1000
  56 }