src/mainboard/intel/glkrvp/ec.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <arch/io.h>
   5 #include <console/console.h>
   6 #include <ec/ec.h>
   7 #include <ec/google/chromeec/ec.h>
   8 #include <intelblocks/lpc_lib.h>
   9 #include <variant/ec.h>
  10
  11 static void ramstage_ec_init(void)
  12 {
  13         const struct google_chromeec_event_info info = {
  14                 .log_events = MAINBOARD_EC_LOG_EVENTS,
  15                 .sci_events = MAINBOARD_EC_SCI_EVENTS,
  16                 .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
  17                 .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
  18                 .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
  19         };
  20
  21         printk(BIOS_INFO, "mainboard: EC init\n");
  22
  23         google_chromeec_events_init(&info, acpi_is_wakeup_s3());
  24 }
  25
  26 static void bootblock_ec_init(void)
  27 {
  28         uint16_t ec_ioport_base;
  29         size_t ec_ioport_size;
  30
  31         /*
  32          * Set up LPC decoding for the ChromeEC I/O port ranges:
  33          * - Ports 62/66, 60/64, and 200->208
  34          * - ChromeEC specific communication I/O ports.
  35          */
  36         lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
  37                 | LPC_IOE_LGE_200);
  38         google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
  39         lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
  40 }
  41
  42 void mainboard_ec_init(void)
  43 {
  44         if (CONFIG(EC_GOOGLE_CHROMEEC)) {
  45                 if (ENV_RAMSTAGE)
  46                         ramstage_ec_init();
  47                 else if (ENV_BOOTBLOCK)
  48                         bootblock_ec_init();
  49         } else if (ENV_BOOTBLOCK) {
  50                 /*
  51                  * Set up LPC decoding for the ChromeEC I/O port ranges:
  52                  * - Ports 62/66, 60/64, and 200->208
  53                  * - ChromeEC specific communication I/O ports.
  54                  */
  55                 lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
  56                         | LPC_IOE_LGE_200);
  57         }
  58
  59         if (CONFIG(GLK_INTEL_EC)) {
  60                 printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa,0x66)\n");
  61                 outb(0xaa, 0x66);
  62                 printk(BIOS_INFO, "Hack to turn on the CPU fan\n");
  63                 outb(0x81, 0x66);
  64                 outb(0x44, 0x62);
  65                 outb(0x32, 0x62);
  66                 /* Need delay here, hence second outb */
  67                 outb(0x32, 0x62);
  68                 outb(0x1a, 0x66);
  69         }
  70 }