src/mainboard/intel/jasperlake_rvp/chromeos.fmd

   1 FLASH@0xff000000 0x1000000 {
   2         SI_ALL@0x0 0x381000 {
   3                 SI_DESC@0x0 0x1000
   4                 SI_EC@0x1000 0x80000
   5                 SI_ME@0x81000 0x300000
   6         }
   7         SI_BIOS@0x381000 0xc7f000 {
   8                 RW_LEGACY(CBFS)@0x0 0x100000
   9                 RW_SECTION_A@0x100000 0x3a4800 {
  10                         VBLOCK_A@0x0 0x2000
  11                         FW_MAIN_A(CBFS)@0x2000 0x2127c0
  12                         RW_FWID_A@0x2147c0 0x40
  13                         ME_RW_A(CBFS)@0x214800 0x190000
  14                 }
  15                 RW_SECTION_B@0x4a4800 0x3a4800 {
  16                         VBLOCK_B@0x0 0x2000
  17                         FW_MAIN_B(CBFS)@0x2000 0x2127c0
  18                         RW_FWID_B@0x2147c0 0x40
  19                         ME_RW_B(CBFS)@0x214800 0x190000
  20                 }
  21                 RW_MISC@0x849000 0x36000 {
  22                         UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {
  23                                 RECOVERY_MRC_CACHE@0x0 0x10000
  24                                 RW_MRC_CACHE@0x10000 0x20000
  25                         }
  26                         RW_ELOG(PRESERVE)@0x30000 0x1000
  27                         RW_SHARED@0x31000 0x1000 {
  28                                 SHARED_DATA@0x0 0x1000
  29                         }
  30                         RW_VPD(PRESERVE)@0x32000 0x2000
  31                         RW_NVRAM(PRESERVE)@0x34000 0x2000
  32                 }
  33                 # Make WP_RO region align with SPI vendor
  34                 # memory protected range specification.
  35                 WP_RO@0x87f000 0x400000 {
  36                         RO_VPD(PRESERVE)@0x0 0x4000
  37                         RO_SECTION@0x4000 0x3fc000 {
  38                                 FMAP@0x0 0x800
  39                                 RO_FRID@0x800 0x40
  40                                 RO_FRID_PAD@0x840 0x7c0
  41                                 GBB@0x1000 0x3000
  42                                 COREBOOT(CBFS)@0x4000 0x3f8000
  43                         }
  44                 }
  45         }
  46 }