src/mainboard/intel/mtlrvp/chromeos.fmd

   1 FLASH 32M {
   2         SI_ALL 9M {
   3                 SI_DESC 16K
   4                 SI_EC 512K
   5                 SI_ME
   6         }
   7         SI_BIOS 23M {
   8                 RW_SECTION_A 6M {
   9                         VBLOCK_A 64K
  10                         FW_MAIN_A(CBFS)
  11                         RW_FWID_A 64
  12                         ME_RW_A(CBFS) 3008K
  13                 }
  14                 RW_LEGACY(CBFS) 2M
  15                 RW_MISC 1M {
  16                         UNIFIED_MRC_CACHE 128K {
  17                                 RECOVERY_MRC_CACHE 64K
  18                                 RW_MRC_CACHE 64K
  19                         }
  20                         RW_ELOG(PRESERVE) 16K
  21                         RW_SHARED 16K {
  22                                 SHARED_DATA 8K
  23                                 VBLOCK_DEV 8K
  24                         }
  25                         RW_VPD(PRESERVE) 8K
  26                         RW_NVRAM(PRESERVE) 24K
  27                 }
  28                 RW_SECTION_B 6M {
  29                         VBLOCK_B 64K
  30                         FW_MAIN_B(CBFS)
  31                         RW_FWID_B 64
  32                         ME_RW_B(CBFS) 3008K
  33                 }
  34                 # Make WP_RO region align with SPI vendor
  35                 # memory protected range specification.
  36                 WP_RO 8M {
  37                         RO_VPD(PRESERVE) 16K
  38                         RO_SECTION {
  39                                 FMAP 2K
  40                                 RO_FRID 64
  41                                 GBB@4K 12K
  42                                 COREBOOT(CBFS)
  43                         }
  44                 }
  45         }
  46 }