src/mainboard/intel/saddlebrook/devicetree.cb

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/skylake
   4
   5         register "deep_s5_enable_ac" = "0"
   6         register "deep_s5_enable_dc" = "0"
   7         register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
   8
   9         # GPE configuration
  10         # Note that GPE events called out in ASL code rely on this
  11         # route. i.e. If this route changes then the affected GPE
  12         # offset bits also need to be changed.
  13         register "gpe0_dw0" = "GPP_B"
  14         register "gpe0_dw1" = "GPP_D"
  15         register "gpe0_dw2" = "GPP_E"
  16
  17         # FSP Configuration
  18         register "DspEnable" = "1"
  19         register "IoBufferOwnership" = "3"
  20         register "ScsEmmcHs400Enabled" = "0"
  21         register "SkipExtGfxScan" = "1"
  22
  23         # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
  24         # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
  25         register "PmConfigSlpS3MinAssert" = "0x02"
  26
  27         # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
  28         register "PmConfigSlpS4MinAssert" = "0x04"
  29
  30         # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
  31         register "PmConfigSlpSusMinAssert" = "0x03"
  32
  33         # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
  34         register "PmConfigSlpAMinAssert" = "0x03"
  35
  36         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  37
  38         # VR Settings Configuration for 4 Domains
  39         #+----------------+-----------+-----------+-------------+----------+
  40         #| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
  41         #+----------------+-----------+-----------+-------------+----------+
  42         #| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
  43         #| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
  44         #| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
  45         #| Psi3Enable     | 1         | 1         | 1           | 1        |
  46         #| Psi4Enable     | 1         | 1         | 1           | 1        |
  47         #| ImonSlope      | 0         | 0         | 0           | 0        |
  48         #| ImonOffset     | 0         | 0         | 0           | 0        |
  49         #| IccMax         | 7A        | 34A       | 35A         | 35A      |
  50         #| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
  51         #+----------------+-----------+-----------+-------------+----------+
  52         register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
  53                 .vr_config_enable = 1,
  54                 .psi1threshold = VR_CFG_AMP(20),
  55                 .psi2threshold = VR_CFG_AMP(4),
  56                 .psi3threshold = VR_CFG_AMP(1),
  57                 .psi3enable = 1,
  58                 .psi4enable = 1,
  59                 .imon_slope = 0x0,
  60                 .imon_offset = 0x0,
  61                 .icc_max = VR_CFG_AMP(7),
  62                 .voltage_limit = 1520,
  63         }"
  64
  65         register "domain_vr_config[VR_IA_CORE]" = "{
  66                 .vr_config_enable = 1,
  67                 .psi1threshold = VR_CFG_AMP(20),
  68                 .psi2threshold = VR_CFG_AMP(5),
  69                 .psi3threshold = VR_CFG_AMP(1),
  70                 .psi3enable = 1,
  71                 .psi4enable = 1,
  72                 .imon_slope = 0x0,
  73                 .imon_offset = 0x0,
  74                 .icc_max = VR_CFG_AMP(34),
  75                 .voltage_limit = 1520,
  76         }"
  77
  78         register "domain_vr_config[VR_GT_UNSLICED]" = "{
  79                 .vr_config_enable = 1,
  80                 .psi1threshold = VR_CFG_AMP(20),
  81                 .psi2threshold = VR_CFG_AMP(5),
  82                 .psi3threshold = VR_CFG_AMP(1),
  83                 .psi3enable = 1,
  84                 .psi4enable = 1,
  85                 .imon_slope = 0x0,
  86                 .imon_offset = 0x0,
  87                 .icc_max = VR_CFG_AMP(35),
  88                 .voltage_limit = 1520,
  89         }"
  90
  91         register "domain_vr_config[VR_GT_SLICED]" = "{
  92                 .vr_config_enable = 1,
  93                 .psi1threshold = VR_CFG_AMP(20),
  94                 .psi2threshold = VR_CFG_AMP(5),
  95                 .psi3threshold = VR_CFG_AMP(1),
  96                 .psi3enable = 1,
  97                 .psi4enable = 1,
  98                 .imon_slope = 0x0,
  99                 .imon_offset = 0x0,
 100                 .icc_max = VR_CFG_AMP(35),
 101                 .voltage_limit = 1520,
 102         }"
 103
 104         # Enable x1 slot
 105         register "PcieRpEnable[7]" = "1"
 106         register "PcieRpClkReqSupport[7]" = "1"
 107         register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3
 108
 109         # Enable x4 slot
 110         register "PcieRpEnable[8]" = "1"
 111         register "PcieRpClkReqSupport[8]" = "1"
 112         register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4
 113
 114         # Enable Root port 6 and 13.
 115         register "PcieRpEnable[5]" = "1"
 116         register "PcieRpEnable[12]" = "1"
 117
 118         # Enable CLKREQ#
 119         register "PcieRpClkReqSupport[5]" = "1"
 120         register "PcieRpClkReqSupport[12]" = "1"
 121
 122         # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2#
 123         register "PcieRpClkReqNumber[5]" = "0"
 124         register "PcieRpClkReqNumber[12]" = "1"
 125
 126         # USB related
 127         register "SsicPortEnable" = "1"
 128
 129         register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"  # OTG
 130         register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"  # Touch Pad
 131         register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"  # M.2 BT
 132         register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"  # Touch Panel
 133         register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"  # M.2 WWAN
 134         register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"  # Front Panel
 135         register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"  # Front Panel
 136         register "usb2_ports[7]" = "USB2_PORT_MID(OC2)"  # Stacked conn (lan + usb)
 137         register "usb2_ports[8]" = "USB2_PORT_MID(OC2)"  # Stacked conn (lan + usb)
 138         register "usb2_ports[9]" = "USB2_PORT_MID(OC1)"  # LAN MAGJACK
 139         register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
 140         register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor
 141         register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
 142         register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
 143
 144         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG
 145         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
 146         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex
 147         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM
 148         register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
 149         register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
 150         register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
 151         register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
 152         register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
 153         register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
 154
 155         register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"  # I2C4 is 1.8V
 156
 157         # Must leave UART0 enabled or SD/eMMC will not work as PCI
 158
 159         register "SataSalpSupport" = "1"
 160         register "SataPortsEnable" = "{ \
 161                 [0]     = 1, \
 162                 [1]     = 1, \
 163                 [2]     = 1, \
 164                 [3]     = 1, \
 165                 [4]     = 1, \
 166                 [5]     = 1, \
 167                 [6]     = 1, \
 168                 [7]     = 1, \
 169         }"
 170         register "SerialIoDevMode" = "{ \
 171                 [PchSerialIoIndexI2C0]  = PchSerialIoPci, \
 172                 [PchSerialIoIndexI2C1]  = PchSerialIoPci, \
 173                 [PchSerialIoIndexI2C2]  = PchSerialIoPci, \
 174                 [PchSerialIoIndexI2C3]  = PchSerialIoPci, \
 175                 [PchSerialIoIndexI2C4]  = PchSerialIoPci, \
 176                 [PchSerialIoIndexI2C5]  = PchSerialIoPci, \
 177                 [PchSerialIoIndexSpi0]  = PchSerialIoPci, \
 178                 [PchSerialIoIndexSpi1]  = PchSerialIoPci, \
 179                 [PchSerialIoIndexUart0] = PchSerialIoPci, \
 180                 [PchSerialIoIndexUart1] = PchSerialIoPci, \
 181                 [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
 182         }"
 183
 184         # PL2 override 25W
 185         register "power_limits_config" = "{
 186                 .tdp_pl2_override = 25,
 187         }"
 188
 189         # Send an extra VR mailbox command for the PS4 exit issue
 190         register "SendVrMbxCmd" = "2"
 191
 192         # Use default SD card detect GPIO configuration
 193         #register "sdcard_cd_gpio" = "GPP_A7"
 194
 195         device cpu_cluster 0 on
 196                 device lapic 0 on end
 197         end
 198         device domain 0 on
 199                 device pci 00.0 on  end # Host Bridge
 200                 device pci 02.0 on  end # Integrated Graphics Device
 201                 device pci 04.0 off end # SA thermal subsystem
 202                 device pci 14.0 on  end # USB xHCI
 203                 device pci 14.1 off end # USB xDCI (OTG)
 204                 device pci 14.2 on  end # Thermal Subsystem
 205                 device pci 15.0 on  end # I2C #0
 206                 device pci 15.1 on  end # I2C #1
 207                 device pci 15.2 on  end # I2C #2
 208                 device pci 15.3 on  end # I2C #3
 209                 device pci 16.0 on  end # Management Engine Interface 1
 210                 device pci 16.1 off end # Management Engine Interface 2
 211                 device pci 16.2 off end # Management Engine IDE-R
 212                 device pci 16.3 off end # Management Engine KT Redirection
 213                 device pci 16.4 off end # Management Engine Interface 3
 214                 device pci 17.0 on end # SATA
 215                 device pci 19.0 on  end # UART #2
 216                 device pci 19.1 on  end # I2C #5
 217                 device pci 19.2 on  end # I2C #4
 218                 device pci 1c.0 on  end # PCI Express Port 1
 219                 device pci 1c.1 off end # PCI Express Port 2
 220                 device pci 1c.2 off end # PCI Express Port 3
 221                 device pci 1c.3 off end # PCI Express Port 4
 222                 device pci 1c.4 off end # PCI Express Port 5
 223                 device pci 1c.5 off end # PCI Express Port 6
 224                 device pci 1c.6 off end # PCI Express Port 7
 225                 device pci 1c.7 off end # PCI Express Port 8
 226                 device pci 1d.0 off end # PCI Express Port 9
 227                 device pci 1d.1 off end # PCI Express Port 10
 228                 device pci 1d.2 off end # PCI Express Port 11
 229                 device pci 1d.3 off end # PCI Express Port 12
 230                 device pci 1e.0 on  end # UART #0
 231                 device pci 1e.1 on  end # UART #1
 232                 device pci 1e.2 on  end # GSPI #0
 233                 device pci 1e.3 on  end # GSPI #1
 234                 device pci 1e.4 off  end # eMMC
 235                 device pci 1e.5 off  end # SDIO
 236                 device pci 1e.6 off  end # SDCard
 237                 device pci 1f.0 on
 238                 end # LPC Interface
 239                 device pci 1f.1 on  end # P2SB
 240                 device pci 1f.2 on  end # Power Management Controller
 241                 device pci 1f.3 on  end # Intel HDA
 242                 device pci 1f.4 on  end # SMBus
 243                 device pci 1f.5 on  end # PCH SPI
 244                 device pci 1f.6 on end # GbE
 245         end
 246 end