src/mainboard/intel/strago/chromeos.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootmode.h>
   4 #include <boot/coreboot_tables.h>
   5 #include <gpio.h>
   6 #include <types.h>
   7 #include <vendorcode/google/chromeos/chromeos.h>
   8
   9 #include "onboard.h"
  10
  11 void fill_lb_gpios(struct lb_gpios *gpios)
  12 {
  13         struct lb_gpio chromeos_gpios[] = {
  14                 {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
  15                 {-1, ACTIVE_HIGH, 0, "power"},
  16                 {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
  17         };
  18         lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
  19 }
  20
  21 int get_write_protect_state(void)
  22 {
  23         /*
  24          * This function might get queried early in romstage. The GPIOs have
  25          * not been set up yet as that configuration is done in ramstage.
  26          * Configuring this GPIO as input so that there isn't any ambiguity
  27          * in the reading.
  28          */
  29         if (ENV_ROMSTAGE_OR_BEFORE)
  30                 gpio_input_pullup(WP_GPIO);
  31
  32         /* WP is enabled when the pin is reading high. */
  33         return !!gpio_get(WP_GPIO);
  34 }
  35
  36 static const struct cros_gpio cros_gpios[] = {
  37         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
  38         CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME),
  39 };
  40
  41 DECLARE_CROS_GPIOS(cros_gpios);